C28 General-Purpose Input/Output (GPIO)
450
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
General-Purpose Input/Output (GPIO)
4.2.7.42 GPIO Port E Data (GPEDAT) Register
The GPIO Port E Data (GPEDAT) register is shown and described in the figure and table below.
Figure 4-83. GPIO Port E Data (GPEDAT) Register
31
16
Resrerved
R-0
15
8
Reserved
R-0
7
6
5
4
3
2
1
0
GPIO135
GPIO134
GPIO133
GPIO132
GPIO131
GPIO130
GPIO129
GPIO128
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 4-92. GPIO Port E Data (GPEDAT) Register Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
Any writes to these bit(s) must always have a value of 0.
7-0
GPIO135-GPIO128
Each bit corresponds to one GPIO port E pin (GPIO128-GPIO135)
0
Reading a 0 indicates that the state of the pin is currently low, irrespective of the mode the pin is
configured for.
Writing a 0 will force an output of 0 if the pin is configured as a GPIO output in the appropriate
GPEMUX1 and GPEDIR registers; otherwise, the value is latched but not used to drive the pin.
1
Reading a 1 indicates that the state of the pin is currently high irrespective of the mode the pin is
configured for.
Writing a 1 will force an output of 1 if the pin is configured as a GPIO output in the GPEMUX1
and GPEDIR registers; otherwise, the value is latched but not used to drive the pin.