Texas Instruments Concerto F28M36 Series, Technical Reference Manual

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Register Descriptions
1499 SPRUHE8E – October 2012 – Revised November 2019
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Copyright © 2012–2019, Texas Instruments Incorporated
M3 Universal Asynchronous Receivers/Transmitters (UARTs)
Figure 21-7. UART Data Register (UARTDR)
31 16
Reserved
R-0
15 12 11 10 9 8 7 0
Reserved OE BE PE FE DATA
R-0 R-0 R-0 R-0 R-0 R/W-0x00
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 21-2. UART Data Register (UARTDR) Field Descriptions
Bit Field Value Description
31-12 Reserved Reseved
11 OE UART Overrun Error
0 No data has been lost due to a FIFO overrun.
1 New data was received when the FIFO was full, resulting in data loss.
10 BE UART Break Error
In FIFO mode, this error is associated with the character at the top of the FIFO. When a break
occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the
received data input goes to a 1 (marking state), and the next valid start bit is received.
0 No break condition has occurred.
1 A break condition has been detected, indicating that the receive data input was held Low for longer
than a full-word transmission time (defined as start, data, parity, and stop bits).
9 PE UART Parity Error
In FIFO mode, this error is associated with the character at the top of the FIFO.
0 No parity error has occurred.
1 The parity of the received data character does not match the parity defined by bits 2 and 7 of the
UARTLCRH register.
8 FE UART Framing Error
0 No framing error has occurred.
1 The received character does not have a valid stop bit (a valid stop bit is 1).
7-0 DATA Data Transmitted or Received
Data that is to be transmitted via the UART is written to this field.When read, this field contains the
data that was received by the UART.
21.7.2 UART Receive Status/Error Clear Register (UARTRSR/UARTECR), offset 0x004
The UARTRSR/UARTECR register is the receive status register/error clear register.
In addition to the UARTDR register, receive status can also be read from the UARTRSR register. If the
status is read from this register, then the status information corresponds to the entry read from UARTDR
prior to reading UARTRSR. The status information for overrun is set immediately when an overrun
condition occurs.
The UARTRSR register cannot be written.
A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors. All the
bits are cleared on reset.
READ-ONLY Status Register