Pad
Control
Commit
Control
Mode
Control
GPIOAFSEL
Data
Control
Interrupt
Control
MUX
MUX
DEMUX
Digital
I/O
Pad
Identification Registers
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
Pad Input
Pad Output
Enable
GPIOLOCK
GPIOCR
GPIODATA
GPIODIR
GPIOIS
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
GPIOPUR
GPIOODR
GPIODEN
Alternate Input
Alternate Output
Alternate OutputEnable
Interrupt
GPIO Input
GPIO Output
GPIO OutputEnable
Pad Output
Package I/OPin
MUX
Periph 0
Periph 1
Periph n
Port
Control
GPIOPCTL
GPIOAPSEL
GPIOAMSEL
GPIOCSEL
General-Purpose Input/Output (GPIO)
351
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
General-Purpose Input/Output (GPIO)
The M3 GPIO Mux also contains an alternate muxing mode. The proper bits in the Alternate Peripheral
Select (GPIOAPSEL) register must be set to access these muxing options. The Digital Function
(GPIOPCTL) register can then be used to select the mux option.
4.1.3 Functional Description
Each GPIO port is a separate hardware instantiation of the same physical block (see
). The
microcontroller contains nine ports and therefore nine of these physical GPIO blocks. Note that not all pins
may be implemented on every block. Some GPIO pins can function as I/O signals for the on-chip
peripheral modules.
Figure 4-1. Digital I/O Pads
4.1.3.1
Master Control
The M3 GPIO mux is the master, and at boot time, the user needs to allocate which core (M3 or C28)
controls which pin. By default, all pins are assigned to the M3 GPIO mux except Group 2 GPIOs. See
for more information.
To select which core controls a GPIO pin, use the GPIO Core Select (GPIOCSEL) register. If the M3
GPIOs are enabled by the GPIODEN register, the M3 can still monitor any GPIO, even if it is mapped to
the C28 GPIO mux.