24
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
List of Figures
1-48.
Control Subsystem Peripheral Configuration 4 (CCNF4) Register
.................................................
1-49.
Master Subsystem Memory Configuration (MEMCNF) Register
...................................................
1-50.
Subsystem Reset Configuration/Control (CRESCNF) Register
....................................................
1-51.
Control Subsystem Reset Status (CRESSTS) Register
.............................................................
1-52.
Master Reset Cause (MRESC) Register
..............................................................................
1-53.
C28 Reset Cause Register (CRESC) Register
.......................................................................
1-54.
Software Reset Control 0 (SRCR0) Register
.........................................................................
1-55.
Software Reset Control 1 (SRCR1) Register
.........................................................................
1-56.
Software Reset Control 2 (SRCR2) Register
.........................................................................
1-57.
Software Reset Control 3 (SRCR3) Register
.........................................................................
1-58.
General-Purpose Input/Output Software Reset Control (SRGPIO) Register
.....................................
1-59.
Master Subsystem Wait-In-Reset (MWIR) Register
..................................................................
1-60.
C28 Wait-In-Reset (CWIR) Register
...................................................................................
1-61.
M3NMI Configuration (MNMICFG) Register
..........................................................................
1-62.
M3NMI Flag (MNMIFLG) Register
......................................................................................
1-63.
M3NMI Flag Clear (MNMIFLGCLR) Register
.........................................................................
1-64.
M3NMI Flag Force (MNMIFLGFRC) Register
........................................................................
1-65.
M3NMI Watchdog Counter (MNMIWDCNT) Register
................................................................
1-66.
M3NMI Watchdog Period (MNMIWDPRD) Register
.................................................................
1-67.
C28 NMI Configuration (CNMICFG) Register
.........................................................................
1-68.
C28 NMI Flag (CNMIFLG) Register
....................................................................................
1-69.
C28 NMI Flag Clear (CNMIFLGCLR) Register
.......................................................................
1-70.
C28 NMI Flag Force (CNMIFLGFRC) Register
.......................................................................
1-71.
C28 NMI Watchdog Counter (CNMIWDCNT) Register
..............................................................
1-72.
C28 NMI Watchdog Period (CNMIWDPRD) Register
...............................................................
1-73.
PIE, Control (PIECTRL) Register
.......................................................................................
1-74.
PIE, Acknowledge (PIEACK) Register
.................................................................................
1-75.
PIE, INTx Group Enable Register (PIEIERx) (x = 1 to 12)
..........................................................
1-76.
PIE, INTx Group Flag Register (PIEIFRx) (x = 1 to 12)
.............................................................
1-77.
CPU Interrupt Flag Register (IFR)
......................................................................................
1-78.
CPU Interrupt Enable Register (IER)
...................................................................................
1-79.
Debug Interrupt Enable Register (DBGIER)
..........................................................................
1-80.
C28 External Interrupt 1 Configuration Register (XINT1CR)
........................................................
1-81.
C28 External Interrupt 2 Configuration Register (XINT2CR)
........................................................
1-82.
C28 External Interrupt 3 Configuration Register (XINT3CR)
........................................................
1-83.
C28 External Interrupt 1 Counter Register (XINT1CTR)
............................................................
1-84.
C28 External Interrupt 2 Counter Register (XINT2CTR)
............................................................
1-85.
C28 External Interrupt 3 Counter Register (XINT3CTR)
............................................................
1-86.
System PLL Configuration (SYSPLLCTL) Register
..................................................................
1-87.
Control Subsystem Clock Disable (CCLKOFF) Register
............................................................
1-88.
M3 Configuration Write Allow (MWRALLOW) Register
..............................................................
1-89.
M3 Configuration Lock (MLOCK) Register
............................................................................
1-90.
Missing Clock Status (MCLKSTS) Register
...........................................................................
1-91.
Missing Clock Force (MCLKFRCCLR) Register
......................................................................
1-92.
Missing Clock Enable (MCLKEN) Register
............................................................................
1-93.
Missing Clock Reference Limit (MCLKLIMIT) Register
..............................................................
1-94.
C28 USER_SWREG1 Register
.........................................................................................
1-95.
C28_USER_SWREG2 Register
........................................................................................
1-96.
System PLL Multiplier (SYSPLLMULT) Register
.....................................................................