General-Purpose Mode
1253
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
External Peripheral Interface (EPI)
NOTE:
If general purpose mode is configured to 32-bit data transfers (DSIZE = 0x3 in the EPICFG
register), CLKPIN must be set to 0 to prevent clock-gated reads.
•
Use of the ready input (iRDY) from the external device is controlled by the RDYEN bit in the
EPIGPCFG register. The iRDY signal uses EPI0S27 and may only be used with a free-running clock.
iRDY gates transactions, no matter what state they are in. When iRDY is deasserted, the transaction is
held off from completing.
•
Use of the frame output (FRAME) is controlled by the FRMPIN bit in the EPIGPCFG register. The
frame pin maybe used whether the clock is output or not, and whether the clock is free running or not.
It may also be used along with the iRDY signal. The frame may be a pulse (one clock) or may be
50/50 split across the frame size (controlled by the FRM50 bit in the EPIGPCFG register). The frame
count (the size of the frame as specified by the FRMCNT field in the EPIGPCFG register) may be
between 1 and 15 clocks for pulsed and between 2 and 30 clocks for 50/50. The frame pin counts
transactions and not clocks; a transaction is any clock where the RD or WR strobe is high (if used). So,
if the FRMCNT bit is set, then the frame pin pulses every other transaction; if 2-cycle reads and writes
are used, it pulses every other address phase. FRM50 must be used with this in mind as it may hold
state for many clocks waiting for the next transaction.
•
Use of the RD and WR outputs is controlled by the RW bit in the EPIGPCFG register. For interfaces
where the direction is known (in advance, related to frame size, or other means), these strobes are not
needed. For most other interfaces, RD and WR are used so the external peripheral knows what
transaction is taking place, and if any transaction is taking place.
•
Separation of address/request and data phases may be used on writes using the WR2CYC bit in the
EPIGPCFG register. This configuration allows the external peripheral extra time to act. Address and
data phases must be separated on reads, and the RD2CYC bit in the EPIGPCFG register must be set.
When configured to use an address as specified by the ASIZE field in the EPIGPCFG register, the
address is emitted on the with the RD strobe (first cycle) and data is expected to be returned on the
next cycle (when RD is not asserted). If no address is used, then RD is asserted on the first cycle and
data is captured on the second cycle (when RD is not asserted), allowing more setup time for data.
For writes, the output may be in one or two cycles. In the two-cycle case, the address (if any) is
emitted on the first cycle with the WR strobe and the data is emitted on the second cycle (with WR not
asserted). Although split address and write data phases are not normally needed for logic reasons, it
may be useful to make read and write timings match. If 2-cycle reads or writes are used, the RW bit is
automatically set.
•
Address may be emitted (controlled by the ASIZE field in the EPIGPCFG register). The address may
be up to 4 bits (16 possible values), up to 12 bits (4096 possible values), or up to 20 bits (1 M possible
values). Size of address limits size of data, for example, 4 bits of address support up to 24 bits data. 4-
bit address uses EPI0S[27:24]; 12-bit address uses EPI0S[27:16]; 20-bit address uses EPI0S[27:8].
The address signals may be used by the external peripheral as an address, code (command), or for
other unrelated uses (such as a chip enable). If the chosen address/data combination does not use all
of the EPI signals, the unused pins can be used as GPIOs or for other functions. For example, when
using a 4-bit address with an 8-bit data, the pins assigned to EPIS0[23:8] can be assigned to other
functions.
•
Data may be 8 bits, 16 bits, 24 bits, or 32 bits (controlled by the DSIZE field in the EPIGPCFG
register).32-bit data cannot be used with address or EPI clock or any other signal. 24-bit data can only
be used with 4-bit address or no address. 32-bit data requires that either the WR2CYC bit or the
RD2CYC bit in the EPIGPCFG register is set.
•
Memory can be used more efficiently by using the Word Access Mode. By default, the EPI controller
uses data bits [7:0] when the DSIZE field in the EPIGPCFG register is 0x0; data bits [15:0] when the
DSIZE field is 0x1; data bits [23:0] when the DSIZE field is 0x2; and data bits [31:0] when the DSIZE
field is 0x3. When the WORD bit in the EPIGPCFG2 register is set, the EPI controller automatically
routes bytes of data onto the correct byte lanes such that data can be stored in bits [31:8] for
DSIZE=0x0 and bits [31:16] for DSIZE=0x1.
•
When using the EPI controller as a GPIO interface, writes are FIFOed (up to 4 can be held at any
time), and up to 32 pins are changed using the EPIBAUD clock rate specified by COUNT0. As a result,
output pin control can be very precisely controlled as a function of time. By contrast, when writing to
normal GPIOs, writes can only occur 8-bits at a time and take up to two clock cycles to complete. In
addition, the write itself may be further delayed by the bus due to
μ
DMA or draining of a previous write.
With both GPIO and the EPI controller, reads may be performed directly, in which case the current pin
