Functional Description
1449
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
M3 Synchronous Serial Interface (SSI)
20.3.1 Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output clock.
Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by peripheral
devices.
The serial bit rate is derived by dividing-down the input clock (CMCLK). The clock is first divided by an
even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register. The clock is further divided by a value from 1 to 256, which is 1 + SCR, where SCR
is the value programmed in the SSI Control 0 (SSICR0) register.
The frequency of the output clock SSIClk is defined by:
SSIClk = CMCLK / (CPSDVSR * (1 + SCR))
NOTE:
For master mode, the system clock must be at least two times faster than the SSIClk, with
the restriction that SSIClk cannot be faster than (CMCLK/2). For slave mode, the system
clock must be at least 12 times faster than the SSIClk. In slave mode, maximum frequency
of operation is (CMCLK/12).
See the
Electrical Characteristics
chapter in the device datasheet to view SSI timing parameters.
20.3.2 FIFO Operation
20.3.2.1 Transmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The CPU
writes data to the FIFO by writing the SSI Data (SSIDR) register, and data is stored in the FIFO until it is
read out by the transmission logic.
When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial
conversion and transmission to the attached slave or master, respectively, through the SSITx pin.
In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit FIFO is
empty and the master initiates, the slave transmits the eighth most recent value in the transmit FIFO. If
less than eight values have been written to the transmit FIFO since the SSI module clock was enabled
using the SSI bit in the CMPCLKCR0 register, then 0 is transmitted. Take care to ensure that valid data is
in the FIFO as needed. The SSI can be configured to generate an interrupt or a µDMA request when the
FIFO is empty.
20.3.2.2 Receive FIFO
The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. Received
data from the serial interface is stored in the buffer until read out by the CPU, which accesses the read
FIFO by reading the SSIDR register.
When configured as a master or slave, serial data received through the SSIRx pin is registered prior to
parallel loading into the attached slave or master receive FIFO, respectively.
When receiving data in master mode, a dummy write to the SSIDR register must occur before any read
occurs.
20.3.3 Interrupts
The SSI can generate interrupts when the following conditions are observed:
•
Transmit FIFO service (when the transmit FIFO is half full or less)
•
Receive FIFO service (when the receive FIFO is half full or more)
•
Receive FIFO time-out
•
Receive FIFO overrun
•
End of transmission
