Register Descriptions
1289
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
External Peripheral Interface (EPI)
The other way to read data is via the address mapped locations (see the EPIADDRMAP register), but this
method is blocking (core or µDMA waits until result is returned).
To cancel a non-blocking read, clear this register. To make sure that all values read are drained from the
NBRFIFO, the EPISTAT register must be consulted to be certain that bits NBRBUSY and ACTIVE are
cleared. One of these registers should not be cleared until either the other EPIRPSTDn register becomes
active or the external interface is not busy. At that point, the corresponding EPIRADDRn register indicates
how many values were read.
Figure 17-41. EPI Non-Blocking Read Data 0 (EPIRPSTD0) Register [offset 0x028] and
EPI Non-Blocking Read Data 1 (EPIRPSTD1) Register [offset 0x038]
31
13 12
0
Reserved
POSTCNT
R-0x0000.0
R/W-0x000
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 17-27. EPI Non-Blocking Read Data 0 (EPIRPSTD0) Register and
EPI Non-Blocking Read Data 1 (EPIRPSTD1) Register Field Descriptions
Bit
Field
Value
Description
31-13
Reserved
Reserved
12-0
POSTCNT
Post Count
A write of a non-zero value starts a read operation for that count. Note that it is the software's
responsibility to handle address wraparound. Reading this register provides the current count.
A write of 0 cancels a non-blocking read (whether active now or pending).Prior to writing a non-zero
value, this register must first be cleared.
