Texas Instruments Concerto F28M36 Series, Technical Reference Manual

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Instruction Set Summary
1633 SPRUHE8E – October 2012 – Revised November 2019
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Copyright © 2012–2019, Texas Instruments Incorporated
Cortex-M3 Processor
Table 24-21. Cortex-M3 Instruction Summary (continued)
Mnemonic Operands Brief Description Flags
LDR Rt , [ Rn {, #offset}] Load register with word -
LDRB, LDRBT Rt , [ Rn {, #offset}] Load register with byte -
LDRD Rt , Rt2 , [ Rn {, #offset}] Load register with two words -
LDREX Rt , [ Rn , #offset ] Load register exclusive -
LDREXB Rt, [Rn]
Load register exclusive with
byte
-
LDREXH Rt , [Rn]
Load register exclusive with
halfword
-
LDRH, LDRHT Rt , [ Rn{ , #offset}] Load register with halfword -
LDRSB, LDRSBT Rt , [ Rn{ , #offset}] Load register with signed byte -
LDRSH, LDRSHT Rt , [ Rn {, #offset}]
Load register with signed
halfword
-
LDRT Rt , [ Rn {, #offset}] Load register with word -
LSL, LSLS Rd , Rm , <Rs|#n> Logical shift left N,Z,C
LSR, LSRS Rd , Rm , <Rs|#n> Logical shift right N,Z,C
MLA Rd , Rn , Rm, Ra
Multiply with accumulate, 32-bit
result
-
MLS Rd , Rn , Rm, Ra
Multiply and subtract, 32-bit
result
-
MOV, MOVS Rd , Op2 Move N,Z,C
MOV, MOVW Rd , #imm16 Move 16-bit constant N,Z,C
MOVT Rd , #imm16 Move top -
MRS Rd , spec_reg
Move from special register to
general register
-
MSR spec_reg , Rn
Move from general register to
special register
N,Z,C,V
MUL, MULS {Rd,}Rn , Rm Multiply, 32-bit result N,Z
MVN, MVNS Rd , Op2 Move NOT N,Z,C
NOP - No operation -
ORN, ORNS {Rd,} Rn , Op2 Logical OR NOT N,Z,C
ORR, ORRS {Rd,} Rn , Op2 Logical OR N,Z,C
POP reglist Pop registers from stack -
PUSH reglist Push registers onto stack -
RBIT Rd , Rn Reverse bits -
REV Rd , Rn Reverse byte order in a word -
REV16 Rd , Rn
Reverse byte order in each
halfword
-
REVSH Rd , Rn
Reverse byte order in bottom
halfword and sign extend
-
ROR, RORS Rd , Rm , <Rs|#n> Rotate right N,Z,C
RRX, RRXS Rd , Rm Rotate right with extend N,Z,C
RSB, RSBS {Rd,} Rn , Op2 Reverse subtract N,Z,C,V
SBC, SBCS {Rd,} Rn , Op2 Subtract with carry N,Z,C,V
SBFX Rd , Rn , #lsb , #width Signed bit field extract -
SDIV {Rd ,} Rn , Rm Signed divide -
SEV - Send event -
SMLAL RdLo, RdHi, Rn, Rm
Signed multiply with
accumulate (32x32+64), 64-bit
result
-
SMULL RdLo, RdHi, Rn, Rm
Signed multiply (32x32), 64-bit
result
-