I2C Module Registers
1069
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
C28 Inter-Integrated Circuit Module
14.5.10 I2C Data Count Register (I2CCNT)
I2CCNT is a 16-bit register used to indicate how many data bytes to transfer when the I2C module is
configured as a transmitter, or to receive when configured as a master receiver. In the repeat mode (RM =
1), I2CCNT is not used. The bits of I2CCNT are shown and described in
and
,
respectively.
The value written to I2CCNT is copied to an internal data counter. The internal data counter is
decremented by 1 for each byte transferred (I2CCNT remains unchanged). If a STOP condition is
requested in the master mode (STP = 1 in I2CMDR), the I2C module terminates the transfer with a STOP
condition when the countdown is complete (that is, when the last byte has been transferred).
Figure 14-27. I2C Data Count Register (I2CCNT)
15
0
ICDC
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 14-18. I2C Data Count Register (I2CCNT) Field Descriptions
Bit
Field
Value
Description
15-0
ICDC
Data count value. ICDC indicates the number of data bytes to transfer or receive. The value in
I2CCNT is a don’t care when the RM bit in I2CMDR is set to 1.
0000h
The start value loaded to the internal data counter is 65536.
0001h-FFFFh
The start value loaded to internal data counter is 1-65535.
14.5.11 I2C Data Receive Register (I2CDRR)
I2CDRR (see
and
) is a 16-bit register used by the CPU to read received data.
The I2C module can receive a data byte with 1 to 8 bits. The number of bits is selected with the bit count
(BC) bits in I2CMDR. One bit at a time is shifted in from the SDA pin to the receive shift register
(I2CRSR). When a complete data byte has been received, the I2C module copies the data byte from
I2CRSR to I2CDRR. The CPU cannot access I2CRSR directly.
If a data byte with fewer than 8 bits is in I2CDRR, the data value is right-justified, and the other bits of
I2CDRR(7-0) are undefined. For example, if BC = 011 (3-bit data size), the receive data is in I2CDRR(2-
0), and the content of I2CDRR(7-3) is undefined.
When in the receive FIFO mode, the I2CDRR register acts as the receive FIFO buffer.
Figure 14-28. I2C Data Receive Register (I2CDRR)
15
8
7
0
Reserved
DATA
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 14-19. I2C Data Receive Register (I2CDRR) Field Descriptions
Bit
Field
Value
Description
15-8
Reserved
These reserved bit locations are always read as zeros. A value written to this field has no effect.
7-0
DATA
Receive data
14.5.12 I2C Data Transmit Register (I2CDXR)
The CPU writes transmit data to I2CDXR (see
and
). This 16-bit register accepts
a data byte with 1 to 8 bits. Before writing to I2CDXR, specify how many bits are in a data byte by loading
the appropriate value into the bit count (BC) bits of I2CMDR. When writing a data byte with fewer than 8
bits, make sure the value is right-aligned in I2CDXR.
