SPI master (master/slave = 1)
SPI slave (master/slave = 0)
SPIRXBUF.15−0
Serial input buffer
SPIRXBUF
Shift register
(SPIDAT)
SPITXBUF.15−0
Serial transmit buffer
SPITXBUF
Processor 1
SPIDAT.15−0
SPICLK
SPISOMI
SPISTE
SPISIMO
SPICLK
SPISOMI
SPISTE
SPISIMO
Slave in/
master out
SPI
strobe
Slave out/
master in
Serial
clock
SPIRXBUF.15−0
Serial input buffer
SPIRXBUF
Shift register
(SPIDAT)
SPITXBUF.15−0
Serial transmit buffer
SPITXBUF
SPIDAT.15−0
Processor 2
LSB
MSB
LSB
MSB
Enhanced SPI Module Overview
987
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
C28 Serial Peripheral Interface (SPI)
Figure 12-3. SPI Master/Slave Connection
12.1.4.2 SPI Module Slave and Master Operation Modes
The SPI can operate in master or slave mode. The MASTER/SLAVE bit (SPICTL.2) selects the operating
mode and the source of the SPICLK signal.
12.1.4.2.1 Master Mode
In the master mode (MASTER/SLAVE = 1), the SPI provides the serial clock on the SPICLK pin for the
entire serial communications network. Data is output on the SPISIMO pin and latched from the SPISOMI
pin.
The SPIBRR register determines both the transmit and receive bit transfer rate for the network. SPIBRR
can select 125 different data transfer rates.
Data written to SPIDAT or SPITXBUF initiates data transmission on the SPISIMO pin, MSB (most
significant bit) first. Simultaneously, received data is shifted through the SPISOMI pin into the LSB (least
significant bit) of SPIDAT. When the selected number of bits has been transmitted, the received data is
transferred to the SPIRXBUF (buffered receiver) for the CPU to read. Data is stored right-justified in
SPIRXBUF.
When the specified number of data bits has been shifted through SPIDAT, the following events occur:
•
SPIDAT contents are transferred to SPIRXBUF.
•
SPI INT FLAG bit (SPISTS.6) is set to 1.
•
If there is valid data in the transmit buffer SPITXBUF, as indicated by the TXBUF FULL bit in SPISTS,
this data is transferred to SPIDAT and is transmitted; otherwise, SPICLK stops after all bits have been
shifted out of SPIDAT.
•
If the SPI INT ENA bit (SPICTL.0) is set to 1, an interrupt is asserted.
In a typical application, the SPISTE pin serves as a chip-enable pin for a slave SPI device. This pin is
driven low by the master before transmitting data to the slave and is taken high after the transmission is
complete.
12.1.4.2.2 Slave Mode
In the slave mode (MASTER/SLAVE = 0), data shifts out on the SPISOMI pin and in on the SPISIMO pin.
The SPICLK pin is used as the input for the serial shift clock, which is supplied from the external network
master. The transfer rate is defined by this clock. The SPICLK input frequency should be no greater than
the LSPCLK frequency divided by 4.
