C28 General-Purpose Input/Output (GPIO)
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SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
General-Purpose Input/Output (GPIO)
Table 4-59. GPIO Port E MUX 1 (GPEMUX1) Register Field Descriptions (continued)
Bit
Field
Value
Description
13-12
GPIO134
Configure this pin as:
00
GPIO 134 - general purpose I/O 134GPIO (default)
01
EPWM12A
10
Reserved
11
Reserved
11-10
GPIO133
Configure this pin as:
00
GPIO 133 - general purpose I/O 133 GPIO (default)
01
EPWM11B
10
Reserved
11
Reserved
9-8
GPIO132
Configure this pin as:
00
GPIO132- general purpose I/O 132 GPIO (default)
01
EPWM11A
10
Reserved
11
Reserved
7-6
GPIO131
Configure this pin as:
00
GPIO 131 - general purpose I/O 131 GPIO (default)
01
EPWM10B
10
Reserved
11
Reserved
5-4
GPIO130
Configure this pin as:
00
GPIO 130 - general purpose I/O 130 GPIO (default)
01
EPWM10A
10
Reserved
11
Reserved
3-2
GPIO129
Configure this pin as:
00
GPIO 129 - general purpose I/O 129 GPIO (default)
01
EPWM9B
10
Reserved
11
Reserved
1-0
GPIO128
Configure this pin as:
00
GPIO 128 - general purpose I/O 128 GPIO (default)
01
EPWM9A
10
Reserved
11
Reserved
4.2.7.10 GPIO Port G MUX 1 (GPGMUX1) Register
The GPIO Port G MUX 1 (GPGMUX1) register is shown and described in the figure and table below.
Figure 4-51. GPIO Port G MUX 1 (GPGMUX1) Register
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIO199
GPIO198
GPIO197
GPIO196
GPIO195
GPIO194
GPIO193
GPIO192
R/W-0
R/W-0
R/W-0
R/W-0
R/W0
R/W0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset