Texas Instruments Concerto F28M36 Series, Technical Reference Manual

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System Control Registers
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244 SPRUHE8E – October 2012 – Revised November 2019
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System Control and Interrupts
Table 1-129. Sleep Mode Clock Gating Control Register 3 (SCGC3) Field Descriptions
Bit Field Value Description
31-26 Reserved Reserved
25 CAN1 CAN1 Clock Gating Control in Sleep Mode
This bit controls the clock gating for the CAN1 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
24 CAN0 CAN0 Clock Gating Control in Sleep Mode
This bit controls the clock gating for the CAN0 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
23-1 Reserved Reserved
0 UART4 UART4 Clock Gating Control in Sleep Mode
This bit controls the clock gating for the UART4 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
1.13.7.24 Deep Sleep Mode Clock Gating Control Register 3 (DCGC3)
Figure 1-119. Deep Sleep Mode Clock Gating Control Register 3 (DCGC3)
31 26 25 24 23 16
Reserved CAN1 CAN0 Reserved
R-0:0 R/W-0 R/W-0 R-0:0
15 1 0
Reserved UART4
R-0:0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 1-130. Deep Sleep Mode Clock Gating Control Register 3 (DCGC3) Field Descriptions
Bit Field Value Description
31-26 Reserved Reserved
25 CAN1 CAN1 Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the CAN1 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
24 CAN0 CAN0 Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the CAN0 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
23-1 Reserved Reserved
0 UART4 UART4 Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the UART4 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
1.13.7.25 General-Purpose Run Mode Clock Gating Control Register (RCGCGPIO)
The RCGCGPIO register provides software the capability to enable and disable GPIO modules in run
mode. When enabled, the GPIO module is provided a clock and accesses to registers are allowed. When
disabled, the clock is disabled to save power and accesses to module registers generate a bus fault.