Exception Model
1622
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
Cortex-M3 Processor
than reset. NMI is permanently enabled and has a fixed priority of -2. NMIs cannot be masked or
prevented from activation by any other exception or preempted by any exception other than reset. On
Concerto devices, a clock fail condition, C28 NMI watchdog timeout reset, C28 PIE NMI vector fetch
error, and GPIO NMI input trigger, can trigger an NMI condition.
•
Hard Fault.
A hard fault is an exception that occurs because of an error during exception processing,
or because an exception cannot be managed by any other exception mechanism. Hard faults have a
fixed priority of -1, meaning they have higher priority than any exception with configurable priority.
•
Memory Management Fault.
A memory management fault is an exception that occurs because of a
memory protection related fault, including access violation and no match. The MPU or the fixed
memory protection constraints determine this fault, for both instruction and data memory transactions.
This fault is used to abort instruction accesses to Execute Never (XN) memory regions, even if the
MPU is disabled.
•
Bus Fault.
A bus fault is an exception that occurs because of a memory-related fault for an instruction
or data memory transaction such as a prefetch fault or a memory access fault. This fault can be
enabled or disabled. On Concerto devices, RAM uncorrectable errors (address error, parity error, and
double data error), and flash uncorrectable errors, can trigger a bus default.
•
Usage Fault.
A usage fault is an exception that occurs because of a fault related to instruction
execution, such as:
–
An undefined instruction
–
An illegal unaligned access
–
Invalid state on instruction execution
–
An error on exception return
An unaligned address on a word or halfword memory access or division by zero can cause a usage
fault when the core is properly configured.
•
SVCall.
A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS
environment, applications can use SVC instructions to access OS kernel functions and device drivers.
•
Debug Monitor.
This exception is caused by the debug monitor (when not halting). This exception is
only active when enabled. This exception does not activate if it is a lower priority than the current
activation.
•
PendSV.
PendSV is a pendable, interrupt-driven request for system-level service. In an OS
environment, use PendSV for context switching when no other exception is active. PendSV is triggered
using the Interrupt Control and State (INTCTRL) register.
•
SysTick.
A SysTick exception is an exception that the system timer generates when it reaches zero
when it is enabled to generate an interrupt. Software can also generate a SysTick exception using the
Interrupt Control and State (INTCTRL) register. In an OS environment, the processor can use this
exception as system tick.
•
Interrupt (IRQ).
An interrupt, or IRQ, is an exception signaled by a peripheral or generated by a
software request and fed through the NVIC (prioritized). All interrupts are asynchronous to instruction
execution. In the system, peripherals use interrupts to communicate with the processor.
lists the interrupts on the controller.
For an asynchronous exception, other than reset, the processor can execute another instruction between
when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that
shows as having configurable priority (see
the SYSHNDCTRL register and the DIS0 register in the
Cortex-M3 Peripherals
chapter.
For more information about hard faults, memory management faults, bus faults, and usage faults, see
