Register Descriptions
1355
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
M3 Universal Serial Bus (USB) Controller
18.5.12 USB FIFO Endpoint n Register (USBFIFO[0]-USBFIFO[15])
NOTE:
Use caution when reading these registers. Performing a read may change bit status.
The USB FIFO endpoint
n
32-bit registers (USBFIFO[
n
]) provide an address for CPU access to the FIFOs
for each endpoint. Writing to these addresses loads data into the Transmit FIFO for the corresponding
endpoint. Reading from these addresses unloads data from the Receive FIFO for the corresponding
endpoint.
Transfers to and from FIFOs can be 8-bit, 16-bit or 32-bit as required, and any combination of accesses is
allowed provided the data accessed is contiguous. All transfers associated with one packet must be of the
same width so that the data is consistently byte-, halfword- or word-aligned. However, the last transfer
may contain fewer bytes than the previous transfers in order to complete an odd-byte or odd-word
transfer.
Depending on the size of the FIFO and the expected maximum packet size, the FIFOs support either
single-packet or double-packet buffering (see
Single-Packet Buffering
in
). Burst writing
of multiple packets is not supported as flags must be set after each packet is written.
Following a STALL response or a transmit error on endpoint 1–15, the associated FIFO is completely
flushed.
For the specific offset for each FIFO register see
Mode(s):
OTG A or Host
OTG B or Device
USBFIFO0-15 are shown in
and described in
Figure 18-17. USB FIFO Endpoint n Register (USBFIFO[n])
31
0
EPDATA
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 18-20. USB FIFO Endpoint n Register (USBFIFO[n]) Field Descriptions
Bit
Field
Reset
Description
31-0
EPDATA
0x0000.0000
Endpoint Data. Writing to this register loads the data into the Transmit FIFO and reading
unloads data from the Receive FIFO.
