Functional Description
1319
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
M3 Universal Serial Bus (USB) Controller
Single-Packet Buffering
If the size of the transmit endpoint's FIFO is less than twice the maximum packet size for this endpoint (as
set in the USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ) register), only one packet can be buffered
in the FIFO and single-packet buffering is required. When each packet is completely loaded into the
transmit FIFO, the TXRDY bit in the USB Transmit Control and Status Endpoint n Low (USBTXCSRLn)
register must be set. If the AUTOSET bit in the USB Transmit Control and Status Endpoint n High
(USBTXCSRHn) register is set, the TXRDY bit is automatically set when a maximum-sized packet is
loaded into the FIFO. For packet sizes less than the maximum, the TXRDY bit must be set manually.
When the TXRDY bit is set, either manually or automatically, the packet is ready to be sent. When the
packet has been successfully sent, both TXRDY and FIFONE are cleared, and the appropriate transmit
endpoint interrupt signaled. At this point, the next packet can be loaded into the FIFO.
Double-Packet Buffering
If the size of the transmit endpoint's FIFO is at least twice the maximum packet size for this endpoint, two
packets can be buffered in the FIFO and double-packet buffering is allowed. As each packet is loaded into
the transmit FIFO, the TXRDY bit in the USBTXCSRLn register must be set. If the AUTOSET bit in the
USBTXCSRHn register is set, the TXRDY bit is automatically set when a maximum-sized packet is loaded
into the FIFO. For packet sizes less than the maximum, TXRDY must be set manually. When the TXRDY
bit is set, either manually or automatically, the packet is ready to be sent. After the first packet is loaded,
TXRDY is immediately cleared and an interrupt is generated. A second packet can now be loaded into the
transmit FIFO and TXRDY set again (either manually or automatically if the packet is the maximum size).
At this point, both packets are ready to be sent. After each packet has been successfully sent, TXRDY is
automatically cleared and the appropriate transmit endpoint interrupt signaled to indicate that another
packet can now be loaded into the transmit FIFO. The state of the FIFONE bit in the USBTXCSRLn
register at this point indicates how many packets may be loaded. If the FIFONE bit is set, then another
packet is in the FIFO and only one more packet can be loaded. If the FIFONE bit is clear, then no packets
are in the FIFO and two more packets can be loaded.
Note:
Double-packet buffering is disabled if an endpoint’s corresponding EPn bit is set in the USB
Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS) register. This bit is set by default, so it
must be cleared to enable double-packet buffering.
18.2.1.1.2 Out Transactions as a Device
When in Device mode, OUT transactions are handled through the USB controller receive FIFOs. The
sizes of the receive FIFOs for the 15 configurable OUT endpoints are determined by the USB Receive
FIFO Start Address (USBRXFIFOADD) register. The maximum amount of data received by an endpoint in
any packet is determined by the value written to the USB Maximum Receive Data Endpoint n
(USBRXMAXPn) register for that endpoint. When double-packet buffering is enabled, two data packets
can be buffered in the FIFO. When double-packet buffering is disabled, only one packet can be buffered
even if the packet is less than half the FIFO size.
Note:
In all cases, the maximum packet size must not exceed the FIFO size.
Single-Packet Buffering
If the size of the receive endpoint FIFO is less than twice the maximum packet size for an endpoint, only
one data packet can be buffered in the FIFO and single-packet buffering is required. When a packet is
received and placed in the receive FIFO, the RXRDY and FULL bits in the USB Receive Control and
Status Endpoint n Low (USBRXCSRL[
n
]) register are set and the appropriate receive endpoint is signaled,
indicating that a packet can now be unloaded from the FIFO. After the packet has been unloaded, the
RXRDY bit must be cleared in order to allow further packets to be received. This action also generates the
acknowledge signaling to the Host controller. If the AUTOCL bit in the USB Receive Control and Status
Endpoint n High (USBRXCSRH[
n
]) register is set and a maximum-sized packet is unloaded from the
FIFO, the RXRDY and FULL bits are cleared automatically. For packet sizes less than the maximum,
RXRDY must be cleared manually.
Double-Packet Buffering
