Texas Instruments Concerto F28M36 Series, Technical Reference Manual

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CEVT1 CEVT2 CEVT3 CEVT4 CEVT1
CAPx pin
0 1 2 3 0 1
XX t
5
XX t
2
XX t
3
XX t
4
t
1
Capture registers [1−4]
All capture values valid
(can be read) at this time
00000000
FFFFFFFF
CTR[0−31] t
1
t
2
t
3
t
4
t
5
MOD4
CTR
CAP1
CAP2
CAP3
CAP4
t
Polarity selection
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Application of the ECAP Module
847 SPRUHE8E – October 2012 – Revised November 2019
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Copyright © 2012–2019, Texas Instruments Incorporated
C28 Enhanced Capture (eCAP) Module
// CAPxPOL bits #define EC_RISING 0x0 #define EC_FALLING 0x1
// CTRRSTx bits #define EC_ABS_MODE 0x0 #define EC_DELTA_MODE 0x1
// PRESCALE bits #define EC_BYPASS 0x0 #define EC_DIV1 0x0 #define EC_DIV2 0x1
#define EC_DIV4 0x2 #define EC_DIV6 0x3
#define EC_DIV8 0x4 #define EC_DIV10 0x5
// ECCTL2 ( ECAP Control Reg 2)
//==========================
// CONT/ONESHOT bit #define EC_CONTINUOUS 0x0 #define EC_ONESHOT 0x1
// STOPVALUE bit #define EC_EVENT1 0x0 #define EC_EVENT2 0x1 #define EC_EVENT3 0x2
#define EC_EVENT4 0x3
// RE-ARM bit #define EC_ARM 0x1
// TSCTRSTOP bit #define EC_FREEZE 0x0 #define EC_RUN 0x1
// SYNCO_SEL bit #define EC_SYNCIN 0x0 #define EC_CTR_PRD 0x1
#define EC_SYNCO_DIS 0x2
// CAP/APWM mode bit #define EC_CAP_MODE 0x0 #define EC_APWM_MODE 0x1
// APWMPOL bit #define EC_ACTV_HI 0x0 #define EC_ACTV_LO 0x1
// Generic #define EC_DISABLE 0x0 #define EC_ENABLE 0x1 #define EC_FORCE 0x1
8.7.1 Example 1 - Absolute Time-Stamp Operation Rising Edge Trigger
Figure 8-23 shows an example of continuous capture operation (Mod4 counter wraps around). In this
figure, TSCTR counts-up without resetting and capture events are qualified on the rising edge only, this
gives period (and frequency) information.
On an event, the TSCTR contents (time-stamp) is first captured, then Mod4 counter is incremented to the
next state. When the TSCTR reaches FFFFFFFF (maximum value), it wraps around to 00000000 (not
shown in
Figure 8-23 ), if this occurs, the CTROVF (counter overflow) flag is set, and an interrupt (if
enabled) occurs, CTROVF (counter overflow) Flag is set, and an Interrupt (if enabled) occurs. Captured
Time-stamps are valid at the point indicated by the diagram (after the 4th event), hence event CEVT4 can
conveniently be used to trigger an interrupt and the CPU can read data from the CAPx registers.
Figure 8-23. Capture Sequence for Absolute Time-stamp and Rising Edge Detect