Texas Instruments Concerto F28M36 Series, Technical Reference Manual

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I2C Module Registers
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1070 SPRUHE8E – October 2012 – Revised November 2019
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C28 Inter-Integrated Circuit Module
After a data byte is written to I2CDXR, the I2C module copies the data byte to the transmit shift register
(I2CXSR). The CPU cannot access I2CXSR directly. From I2CXSR, the I2C module shifts the data byte
out on the SDA pin, one bit at a time.
When in the transmit FIFO mode, the I2CDXR register acts as the transmit FIFO buffer.
Figure 14-29. I2C Data Transmit Register (I2CDXR)
15 8 7 0
Reserved DATA
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 14-20. I2C Data Transmit Register (I2CDXR) Field Descriptions
Bit Field Value Description
15-8 Reserved These reserved bit locations are always read as zeros. A value written to this field has no effect.
7-0 DATA Transmit data
14.5.13 I2C Transmit FIFO Register (I2CFFTX)
The I2C transmit FIFO register (I2CFFTX) is a 16-bit register that contains the I2C FIFO mode enable bit
as well as the control and status bits for the transmit FIFO mode of operation on the I2C peripheral. The
bit fields are shown in
Figure 14-30 and described in Table 14-21 .
Figure 14-30. I2C Transmit FIFO Register (I2CFFTX)
15 14 13 12 11 10 9 8
Reserved I2CFFEN TXFFRST TXFFST4 TXFFST3 TXFFST2 TXFFST1 TXFFST0
R-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0
7 6 5 4 3 2 1 0
TXFFINT TXFFINTCLR TXFFIENA TXFFIL4 TXFFIL3 TXFFIL2 TXFFIL1 TXFFIL0
R-0 R/W1C-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 14-21. I2C Transmit FIFO Register (I2CFFTX) Field Descriptions
Bit Field Value Description
15 Reserved Reserved. Reads will return a 0, writes have no effect.
14 I2CFFEN I2C FIFO mode enable bit. This bit must be enabled for either the transmit or the receive FIFO to
operate correctly.
0 Disable the I2C FIFO mode.
1 Enable the I2C FIFO mode.
13 TXFFRST I2C transmit FIFO reset bit.
0 Reset the transmit FIFO pointer to 0000 and hold the transmit FIFO in the reset state.
1 Enable the transmit FIFO operation.
12-8 TXFFST4-0 Contains the status of the transmit FIFO:
10000 Transmit FIFO contains 16 bytes.
0xxxx Transmit FIFO contains xxxx bytes.
00000 Transmit FIFO is empty.
Note: Since these bits are reset to zero, the transmit FIFO interrupt flag will be set when the
transmit FIFO operation is enabled and the I2C is taken out of reset. This will generate a transmit
FIFO interrupt if enabled. To avoid any detrimental effects from this, write a one to the
TXFFINTCLR once the transmit FIFO operation is enabled and the I2C is taken out of reset.