C28 General-Purpose Input/Output (GPIO)
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SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
General-Purpose Input/Output (GPIO)
port has one clear register. The clear registers always read back 0. If the corresponding pin is
configured as a general purpose output, then writing a 1 to the corresponding bit in the clear register
will clear the output latch and the pin will be driven low. If the pin is not configured as a GPIO output,
then the value will be latched but the pin will not be driven. Only if the pin is later configured as a GPIO
output will the latched value will be driven onto the pin. Writing a 0 to any bit in the clear registers has
no effect.
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GPxTOGGLE/AIOTOGGLE Registers
The toggle registers are used to drive specified GPIO pins to the opposite level without disturbing other
pins. Each I/O port has one toggle register. The toggle registers always read back 0. If the
corresponding pin is configured as an output, then writing a 1 to that bit in the toggle register flips the
output latch and pulls the corresponding pin in the opposite direction. That is, if the output pin is driven
low, then writing a 1 to the corresponding bit in the toggle register will pull the pin high. Likewise, if the
output pin is high, then writing a 1 to the corresponding bit in the toggle register will pull the pin low. If
the pin is not configured as a GPIO output, then the value will be latched but the pin will not be driven.
Only if the pin is later configured as a GPIO output will the latched value will be driven onto the pin.
Writing a 0 to any bit in the toggle registers has no effect.
4.2.5 Input Qualification
The input qualification scheme has been designed to be very flexible. You can select the type of input
qualification for each GPIO pin by configuring the GPxQSEL1 and GPxQSEL2 registers. In the case of a
GPIO input pin, the qualification can be specified as only synchronize to SYSCLKOUT or qualification by a
sampling window. For pins that are configured as peripheral inputs, the input can also be asynchronous in
addition to synchronized to SYSCLKOUT or qualified by a sampling window. The remainder of this section
describes the options available.
4.2.5.1
No Synchronization (asynchronous input)
This mode is used for peripherals where input synchronization is not required or the peripheral itself
performs the synchronization. Examples include communication ports SCI, SPI and I
2
C. In addition, it may
be desirable to have the ePWM trip zone (TZn) signals function independent of the presence of
SYSCLKOUT.
The asynchronous option is not valid if the pin is used as a general purpose digital input pin (GPIO). If the
pin is configured as a GPIO input and the asynchronous option is selected then the qualification defaults
to synchronization to SYSCLKOUT as described in
.
4.2.5.2
Synchronization to SYSCLKOUT Only
This is the default qualification mode of all the pins on GPIO Port A, B, and C. The GPIO pins on Port E
are synchronized to the analog subsystem clock by default. In this mode, the input signal is only
synchronized to the system clock (SYSCLKOUT). Because the incoming signal is asynchronous, it can
take up to a SYSCLKOUT period of delay in order for the input to the DSP to be changed. No further
qualification is performed on the signal.
4.2.5.3
Qualification Using a Sampling Window
In this mode, the signal is first synchronized to the system clock (SYSCLKOUT) and then qualified by a
specified number of cycles before the input is allowed to change.
and
show how
the input qualification is performed to eliminate unwanted noise. Two parameters are specified by the user
for this type of qualification: 1) the sampling period, or how often the signal is sampled, and 2) the number
of samples to be taken.
