Functional Description
1321
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
M3 Universal Serial Bus (USB) Controller
When a Host is attempting to enumerate the USB Device, it requests that the Device change its address
from zero to some other value. The address is changed by writing the value that the Host requested to the
USB Device Functional Address (USBFADDR) register. However, care should be taken when writing to
USBFADDR to avoid changing the address before the transaction is complete. This register should only
be set after the SET_ADDRESS command is complete. Like all control transactions, the transaction is
only complete after the Device has left the STATUS phase. In the case of a SET_ADDRESS command,
the transaction is completed by responding to the IN request from the Host with a zero-byte packet. Once
the Device has responded to the IN request, the USBFADDR register should be programmed to the new
value as soon as possible to avoid missing any new commands sent to the new address.
Note:
If the USBFADDR register is set to the new value as soon as the Device receives the OUT
transaction with the SET_ADDRESS command in the packet, it changes the address during the control
transfer. In this case, the Device does not receive the IN request that allows the USB transaction to exit
the STATUS phase of the control transfer because it is sent to the old address. As a result, the Host does
not get a response to the IN request, and the Host fails to enumerate the Ddvice.
18.2.1.1.5 Device Mode Suspend
When no activity has occurred on the USB bus for 3 ms, the USB controller automatically enters
SUSPEND mode. If the SUSPEND interrupt has been enabled in the USB Interrupt Enable (USBIE)
register, an interrupt is generated at this time. When in SUSPEND mode, the PHY also goes into
SUSPEND mode. When RESUME signaling is detected, the USB controller exits SUSPEND mode and
takes the PHY out of SUSPEND. If the RESUME interrupt is enabled, an interrupt is generated. The USB
controller can also be forced to exit SUSPEND mode by setting the RESUME bit in the USB Power
(USBPOWER) register. When this bit is set, the USB controller exits SUSPEND mode and drives
RESUME signaling onto the bus. The RESUME bit must be cleared after 10 ms (a maximum of 15 ms) to
end RESUME signaling.
To meet USB power requirements, the controller can be put into Deep Sleep mode which keeps the
controller in a static state.
18.2.1.1.6 Start of Frame
When the USB controller is operating in Device mode, it receives a Start-Of-Frame (SOF) packet from the
Host once every millisecond. When the SOF packet is received, the 11-bit frame number contained in the
packet is written into the USB Frame Value (USBFRAME) register, and an SOF interrupt is also signaled
and can be handled by the application. Once the USB controller has started to receive SOF packets, it
expects one every millisecond. If no SOF packet is received after 1.00358 ms, the packet is assumed to
have been lost, and the USBFRAME register is not updated. The USB controller continues and
resynchronizes these pulses to the received SOF packets when these packets are successfully received
again.
18.2.1.1.7 USB Reset
When the USB controller is in device mode and a RESET condition is detected on the USB bus, the USB
controller automatically performs the following actions:
•
Clears the USBFADDR register.
•
Clears the USB Endpoint Index (USBEPIDX) register.
•
Flushes all endpoint FIFOs.
•
Clears all control/status registers.
•
Enables all endpoint interrupts.
•
Generates a RESET interrupt.
