RRDY
DR
FSR
CLKR
Read from DRR1(b)
RBR1 to DRR1 copy(B)
Read from DRR1(A)
RBR1 to DRR1 copy(A)
C5
C6
C7
B0
B1
B2
B3
B4
B5
B6
B7
A0
A1
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DR
RSR[1,2]
Expand
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
RBR[1,2]
DRR[1,2]
DRR[1,2]
RBR[1,2]
To CPU or
DMA controller
justify and bit fill
or
Frame Phases
1084
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
C28 Multichannel Buffered Serial Port (McBSP)
Figure 15-13. McBSP Reception Physical Data Path
A
RSR[1,2]: Receive shift registers 1 and 2
B
RBR[1,2]: Receive buffer registers 1 and 2
C
DRR[1,2]: Data receive registers 1 and 2
Figure 15-14. McBSP Reception Signal Activity
A
CLKR: Internal receive clock
B
FSR: Internal receive frame-synchronization signal
C
DR: Data on DR pin
D
RRDY: Status of receiver ready bit (high is 1)
The following process describes how data travels from the DR pin to the CPU or to the DMA controller:
1. The McBSP waits for a receive frame-synchronization pulse on internal FSR.
2. When the pulse arrives, the McBSP inserts the appropriate data delay that is selected with the
RDATDLY bits of RCR2.
In the preceding timing diagram (
), a 1-bit data delay is selected.
3. The McBSP accepts data bits on the DR pin and shifts them into the receive shift register(s).
If the word length is 16 bits or smaller, only RSR1 is used. If the word length is larger than 16 bits,
RSR2 and RSR1 are used and RSR2 contains the most significant bits. For details on choosing a word
length, see
Set the Receive Word Length(s)
.
4. When a full word is received, the McBSP copies the contents of the receive shift register(s) to the
receive buffer register(s), provided that RBR1 is not full with previous data.
If the word length is 16 bits or smaller, only RBR1 is used. If the word length is larger than 16 bits,
RBR2 and RBR1 are used and RBR2 contains the most significant bits.
5. The McBSP copies the contents of the receive buffer register(s) into the data receive register(s),
provided that DRR1 is not full with previous data. When DRR1 receives new data, the receiver ready
bit (RRDY) is set in SPCR1. This indicates that received data is ready to be read by the CPU or the
DMA controller.
If the word length is 16 bits or smaller, only DRR1 is used. If the word length is larger than 16 bits,
DRR2 and DRR1 are used and DRR2 contains the most significant bits.
If companding is used during the copy (RCOMPAND = 10b or 11b in RCR2), the 8-bit compressed
data in RBR1 is expanded to a left-justified 16-bit value in DRR1. If companding is disabled, the data
copied from RBR[1,2] to DRR[1,2] is justified and bit filled according to the RJUST bits.
6. The CPU or the DMA controller reads the data from the data receive register(s). When DRR1 is read,
RRDY is cleared and the next RBR-to-DRR copy is initiated.
NOTE:
If both DRRs are required (word length larger than 16 bits), the CPU or the DMA controller
must read from DRR2 first and then from DRR1. As soon as DRR1 is read, the next RBR-to-
DRR copy is initiated. If DRR2 is not read first, the data in DRR2 is lost.
When activity is not properly timed, errors can occur. See the following topics for more details:
