Texas Instruments Concerto F28M36 Series, Technical Reference Manual

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Clock
Bus[7:0]
Size
R/W
Addr
15:8
Addr
7:0
Word
15:8
Word
7:0
Read Stall Ready Ready 2-3 Cycle Sync Stall
Digital Buffer
Analog Buffer
Sync Stall
Clock
Bus[7:0]
Size
R/W
Addr
15:8
Addr
7:0
Word 1
15:8
Word 1
7:0
Ready Ready
Word 2
15:8
Word 2
7:0
2-3 Cycle Sync Stall
Digital Buffer
Analog Buffer
Sync Stall
Clock
Bus[7:0]
Size
R/W
Addr
15:8
Addr
7:0
Word
15:8
Word
7:0
Ready Ready 2-3 Cycle Sync Stall
Digital Buffer
Analog Buffer
Sync Stall
Analog Common Interface Bus (ACIB)
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894 SPRUHE8E – October 2012 – Revised November 2019
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Analog Subsystem
The ACIB buffer can store a single write operation from the digital subsystem in order to prevent the CPU
or DMA from stalling on writes. If a second write operation is initiated by the digital subsystem (before the
first write operation completes), the CPU or DMA will stall until the first write operation completes, thereby
freeing up the buffer for the second write operation.
Simplified timing diagrams for ACIB operations are shown in Figure 10-3 to Figure 10-9 . The diagrams are
approximations and may not be cycle accurate.
Figure 10-3. 16-bit Write
Figure 10-4. 32-bit Write
Figure 10-5. 16-bit Read