Register Descriptions
1282
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
External Peripheral Interface (EPI)
Table 17-22. EPI Host-Bus 16 Configuration 2 (EPIHB16CFG2) Register Field Descriptions (continued)
Bit
Field
Value
Description
26
CSBAUD
Chip Select Baud Rate and Multiple Sub-Mode Configuration enable
This bit is only valid when the CS CSCFG field is programmed to 0x2 or 0x3, 0x5 or 0x6.
This bit configures the baud rate settings for CS0, CS1, CS2, and CS3.
This bit must also be set to allow different sub-mode configurations on chip-selects. If this bit is
clear, all chip-select sub-modes are based on the MODE encoding defined in the EPI8HBCFG
register.
If the CSBAUD bit is set in the EPIHBnCFG2 register and dual- or quad-chip selects are enabled,
then the individual chip selects can use different clock frequencies, wait states and strobe polarity.
0
Same Baud Rate and Same Sub-Mode
All CS use the baud rate for the external bus that is defined by the COUNT0 field in the EPIBAUD
register and the sub-mode programmed in the MODE field of the EPIHB16CFG register.
1
Different Baud Rates
CS0 uses the baud rate for the external bus that is defined by the COUNT0 field in the EPIBAUD
register. CS1 uses the baud rate defined by the COUNT1 field in the EPIBAUD register.
CS2 uses the baud rate for the external bus that is defined by the COUNT0 field in the EPIBAUD2
register. CS3 uses the baud rate defined by the COUNT1 field in the EPIBAUD2 register.
In addition, the sub-modes for each chip select are individually programmed in their respective
EPIHB16CFGn registers.
25-24
CSCFG
Chip Select Configuration
This field controls the chip select options, including an ALE format, a single chip select, two chip
selects, and an ALE combined with two chip selects. These bits are also used in combination with
the CSCFGEXT bit for further configurations, including quad- chip select.
0x0
ALE Configuration
EPI0S30 is used as an address latch (ALE). When using this mode, the address and data should
be muxed (HB16MODE field in the EPIHB16CFG register should be configured to 0x0). If needed,
the address can be latched by external logic.
0x1
CS Configuration
EPI0S30 is used as a Chip Select (CS). When using this mode, the address and data should not be
muxed (MODE field in the EPIHB16CFG register should be configured to 0x1). In this mode, the
WR signal (EPI0S29) and the RD signal (EPI0S28) are used to latch the address when CS is low.
0x2
Dual CS Configuration
EPI0S30 is used as CS0 and EPI0S27 is used as CS1. Whether CS0 or CS1 is asserted is
determined by the most significant address bit for a respective external address map. This
configuration can be used for a RAM bank split between 2 devices as well as when using both an
external RAM and an external peripheral.
0x3
ALE with Dual CS Configuration
EPI0S30 is used as address latch (ALE), EPI0S27 is used as CS1, and EPI0S26 is used as CS0.
Whether CS0 or CS1 is asserted is determined by the most significant address bit for a respective
external address map.
23-22
Reserved
Reserved
21
WRHIGH
CS1 WRITE Strobe Polarity
This field is used if CSBAUD bit of the EPIHB16CFG2 register is enabled.
0
The WRITE strobe for CS1 accesses is WR (active Low).
1
The WRITE strobe for CS1 accesses is WR (active High).
20
RDHIGH
CS1 READ Strobe Polarity
This field is used if CSBAUD bit of the EPIHB16CFG2 register is enabled
0
The READ strobe for CS1 accesses is RD (active Low).
1
The READ strobe for CS1 accesses is RD (active High).
19
ALEHIGH
CS1 ALE Strobe Polarity
This field is used if CSBAUD bit of the EPIHB16CFG2 register is enabled
0
The address latch strobe for CS1 accesses is ALE (active Low).
1
The address latch strobe for CS1 accesses is ALE (active High).
18-17
Reserved
Reserved
