NOTE
When the MCG is in BLPI and clocking is derived from the
Fast IRC, the clock divider controls, MCG_SC[FCRDIV] and
SIM_CLKDIV1[OUTDIV4], must be programmed such that
the resulting flash clock nominal frequency is 800 kHz or less.
In this case, one example of correct configuration is
MCG_SC[FCRDIV]=000b and
SIM_CLKDIV1[OUTDIV4]=0100b, resulting in a divide by 5
setting.
5.6 Clock Gating
The clock to each module can be individually gated on and off using the SIM module's
SCGCx registers. These bits are cleared after any reset, which disables the clock to the
corresponding module to conserve power. Prior to initializing a module, set the
corresponding bit in SCGCx register to enable the clock. Before turning off the clock,
make sure to disable the module.
Any bus access to a peripheral that has its clock disabled generates an error termination.
5.7 Module clocks
The following table summarizes the clocks associated with each module.
Table 5-2. Module clocks
Module
Bus interface clock
Internal clocks
I/O interface clocks
Core modules
ARM Cortex-M4 core
System clock
Core clock
—
NVIC
System clock
—
—
DAP
System clock
—
—
ITM
System clock
—
—
cJTAG, JTAGC
—
—
JTAG_CLK
System modules
DMA
System clock
—
—
DMA Mux
Bus clock
—
—
Port control
Bus clock
LPO
—
Crossbar Switch
System clock
—
—
Peripheral bridges
System clock
Bus clock, Flash clock
—
LLWU, PMC, SIM, RCM
Flash clock
LPO
—
Table continues on the next page...
Clock Gating
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
154
Freescale Semiconductor, Inc.
