DMA_CR field descriptions (continued)
Field
Description
3
Reserved
This field is reserved.
2
ERCA
Enable Round Robin Channel Arbitration
0
Fixed priority arbitration is used for channel selection .
1
Round robin arbitration is used for channel selection .
1
EDBG
Enable Debug
0
When in debug mode, the DMA continues to operate.
1
When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to
complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
0
Reserved
This field is reserved.
22.3.2 Error Status Register (DMA_ES)
The ES provides information concerning the last recorded channel error. Channel errors
can be caused by:
• A configuration error, that is:
• An illegal setting in the transfer-control descriptor, or
• An illegal priority register setting in fixed-arbitration
• An error termination to a bus master read or write cycle
See the Error Reporting and Handling section for more details.
Address: 4000_8000h base + 4h offset = 4000_8004h
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_ES field descriptions
Field
Description
31
VLD
Logical OR of all ERR status bits
Table continues on the next page...
Chapter 22 Enhanced Direct Memory Access (eDMA)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
437
