FMC_PFB1CR field descriptions (continued)
Field
Description
00
32 bits
01
64 bits
10
Reserved
11
Reserved
16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7–5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
4
B1DCE
Bank 1 Data Cache Enable
This bit controls whether data references are loaded into the cache.
0
Do not cache data references.
1
Cache data references.
3
B1ICE
Bank 1 Instruction Cache Enable
This bit controls whether instruction fetches are loaded into the cache.
0
Do not cache instruction fetches.
1
Cache instruction fetches.
2
B1DPE
Bank 1 Data Prefetch Enable
This bit controls whether prefetches (or speculative accesses) are initiated in response to data references.
0
Do not prefetch in response to data references.
1
Enable prefetches in response to data references.
1
B1IPE
Bank 1 Instruction Prefetch Enable
This bit controls whether prefetches (or speculative accesses) are initiated in response to instruction
fetches.
0
Do not prefetch in response to instruction fetches.
1
Enable prefetches in response to instruction fetches.
0
B1SEBE
Bank 1 Single Entry Buffer Enable
This bit controls whether the single entry buffer is enabled in response to flash read accesses. Its
operation is independent from bank 0's cache.
A high-to-low transition of this enable forces the page buffer to be invalidated.
0
Single entry buffer is disabled.
1
Single entry buffer is enabled.
Chapter 28 Flash Memory Controller (FMC)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
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