44.4.4.1 Classic SPI Transfer Format (CPHA = 0)
The transfer format shown in following figure is used to communicate with peripheral
SPI slave devices where the first data bit is available on the first clock edge. In this
format, the master and slave sample their SIN pins on the odd-numbered SCK edges and
change the data on their SOUT pins on the even-numbered SCK edges.
t
ASC
= After SCK delay
t
CSC
=
PCS to SCK delay
MSB first (LSBFE = 0): MSB
MSB first (LSBFE = 1): LSB
t
DT =
Delay after Transfer (Minimum CS idle time)
t
CSC
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
t
CSC
t
DT
tASC
PCSx/SS
Slave SOUT
Master SIN/
Master SOUT/
Slave SIN
Master and Slave
Sample
SCK (CPOL = 1)
SCK (CPOL = 0)
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Figure 44-72. Module transfer timing diagram (MTFE=0, CPHA=0, FMSZ=8)
The master initiates the transfer by placing its first data bit on the SOUT pin and asserting
the appropriate peripheral chip select signals to the slave device. The slave responds by
placing its first data bit on its SOUT pin. After the t
ASC
delay elapses, the master outputs
the first edge of SCK. The master and slave devices use this edge to sample the first input
data bit on their serial data input signals. At the second edge of the SCK, the master and
slave devices place their second data bit on their serial data output signals. For the rest of
the frame the master and the slave sample their SIN pins on the odd-numbered clock
edges and changes the data on their SOUT pins on the even-numbered clock edges. After
the last clock edge occurs, a delay of t
ASC
is inserted before the master negates the PCS
signals. A delay of t
DT
is inserted before a new frame transfer can be initiated by the
master.
Chapter 44 Serial Peripheral Interface (SPI)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
1079
