49.1.3.1 Detailed signal description
Table 49-3. GPIO interface-detailed signal descriptions
Signal
I/O
Description
PORTA31–PORTA0
PORTB31–PORTB0
PORTC31–PORTC0
PORTD31–PORTD0
PORTE31–PORTE0
I/O
General-purpose input/output
State meaning
Asserted: The pin is logic 1.
Deasserted: The pin is logic 0.
Timing
Assertion: When output, this
signal occurs on the rising-
edge of the system clock. For
input, it may occur at any time
and input may be asserted
asynchronously to the system
clock.
Deassertion: When output,
this signal occurs on the
rising-edge of the system
clock. For input, it may occur
at any time and input may be
asserted asynchronously to
the system clock.
NOTE
Not all pins within each port are implemented on each device.
See the chapter on signal multiplexing for the number of GPIO
ports available in the device.
49.2 Memory map and register definition
Any read or write access to the GPIO memory space that is outside the valid memory
map results in a bus error.
GPIO memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
400F_F000 Port Data Output Register (GPIOA_PDOR)
32
R/W
0000_0000h
400F_F004 Port Set Output Register (GPIOA_PSOR)
32
W
(always
reads 0)
0000_0000h
400F_F008 Port Clear Output Register (GPIOA_PCOR)
32
W
(always
reads 0)
0000_0000h
400F_F00C Port Toggle Output Register (GPIOA_PTOR)
32
W
(always
reads 0)
0000_0000h
Table continues on the next page...
Chapter 49 General-Purpose Input/Output (GPIO)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
1291
