Freescale Semiconductor MK22FN256VDC12, Reference Manual

Page: 428 / 1313

DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_9094
TCD Signed Destination Address Offset
(DMA_TCD4_DOFF)
16 R/W Undefined 22.3.26/468
4000_9096
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD4_CITER_ELINKYES)
16 R/W Undefined 22.3.27/469
4000_9096 DMA_TCD4_CITER_ELINKNO 16 R/W Undefined 22.3.28/470
4000_9098
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD4_DLASTSGA)
32 R/W Undefined 22.3.29/471
4000_909C TCD Control and Status (DMA_TCD4_CSR) 16 R/W Undefined 22.3.30/472
4000_909E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD4_BITER_ELINKYES)
16 R/W Undefined 22.3.31/474
4000_909E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled) (DMA_TCD4_BITER_ELINKNO)
16 R/W Undefined 22.3.32/475
4000_90A0 TCD Source Address (DMA_TCD5_SADDR) 32 R/W Undefined 22.3.18/462
4000_90A4 TCD Signed Source Address Offset (DMA_TCD5_SOFF) 16 R/W Undefined 22.3.19/462
4000_90A6 TCD Transfer Attributes (DMA_TCD5_ATTR) 16 R/W Undefined 22.3.20/463
4000_90A8
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD5_NBYTES_MLNO)
32 R/W Undefined 22.3.21/464
4000_90A8
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD5_NBYTES_MLOFFNO)
32 R/W Undefined 22.3.22/465
4000_90A8
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD5_NBYTES_MLOFFYES)
32 R/W Undefined 22.3.23/466
4000_90AC
TCD Last Source Address Adjustment
(DMA_TCD5_SLAST)
32 R/W Undefined 22.3.24/467
4000_90B0 TCD Destination Address (DMA_TCD5_DADDR) 32 R/W Undefined 22.3.25/468
4000_90B4
TCD Signed Destination Address Offset
(DMA_TCD5_DOFF)
16 R/W Undefined 22.3.26/468
4000_90B6
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD5_CITER_ELINKYES)
16 R/W Undefined 22.3.27/469
4000_90B6 DMA_TCD5_CITER_ELINKNO 16 R/W Undefined 22.3.28/470
4000_90B8
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD5_DLASTSGA)
32 R/W Undefined 22.3.29/471
4000_90BC TCD Control and Status (DMA_TCD5_CSR) 16 R/W Undefined 22.3.30/472
4000_90BE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD5_BITER_ELINKYES)
16 R/W Undefined 22.3.31/474
4000_90BE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled) (DMA_TCD5_BITER_ELINKNO)
16 R/W Undefined 22.3.32/475
4000_90C0 TCD Source Address (DMA_TCD6_SADDR) 32 R/W Undefined 22.3.18/462
4000_90C4 TCD Signed Source Address Offset (DMA_TCD6_SOFF) 16 R/W Undefined 22.3.19/462
4000_90C6 TCD Transfer Attributes (DMA_TCD6_ATTR) 16 R/W Undefined 22.3.20/463
4000_90C8
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD6_NBYTES_MLNO)
32 R/W Undefined 22.3.21/464
Table continues on the next page...
Memory map/register definition
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
428 Freescale Semiconductor, Inc.