Freescale Semiconductor MK22FN256VDC12, Reference Manual

Page: 131 / 1313

3.9.6 I
2
S configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Signal
multiplexing
Register
access
Peripheral
bridge
Module signals
2
I S
Figure 3-54. I
2
S configuration
Table 3-69. Reference links to related information
Topic Related module Reference
Full description >I
2
S I2S
System memory map System memory map
Clocking Clock Distribution
Power management Power management
Signal multiplexing Port control Signal Multiplexing
3.9.6.1 Instantiation information
This device contains one I
2
S module.
As configured on the device, module features include:
• TX data lines: 1
• RX data lines: 1
• FIFO size (words): 8
• Maximum words per frame: 16
• Maximum bit clock divider: 512
3.9.6.2 I
2
S/SAI clocking
Chapter 3 Chip Configuration
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc. 131