• Trigger input event to pre-trigger m = (prescaler X multiplication factor X delay m) +
2 peripheral clock cycles
• Add 1 additional peripheral clock cycle to determine the time when the channel
trigger output changes.
Each channel is associated with 1 ADC block. PDB channel n pre-trigger outputs 0 to M;
each pre-trigger output is connected to ADC hardware trigger select and hardware trigger
inputs. The pre-triggers are used to precondition the ADC block before the actual trigger
occurs. When the ADC receives the rising edge of the trigger, the ADC will start the
conversion according to the precondition determined by the pre-triggers. The ADC
contains M sets of configuration and result registers, allowing it to alternate conversions
between M different analog sources (like a ping-pong game). The pre-trigger outputs are
used to specify which signal will be sampled next. When a pre-trigger m is asserted, the
ADC conversion is triggered with set m of the configuration and result registers.
The waveforms shown in the following diagram show the pre-trigger and trigger outputs
of PDB channel n. The delays can be independently set using the CHnDLYm registers,
and the pre-triggers can be enabled or disabled in CHnC1[EN[m]].
Trigger input event
Ch
n
pre-trigger 0
Ch
n
pre-trigger 1
Ch
n
pre-trigger
M
Ch
n
trigger
... ... ... ...
Figure 37-50. Pre-trigger and trigger outputs
The delay in CHnDLYm register can be optionally bypassed, if CHnC1[TOS[m]] is
cleared. In this case, when the trigger input event occurs, the pre-trigger m is asserted
after 2 peripheral clock cycles.
The PDB can be configured for back-to-back operation. Back-to-back operation enables
the ADC conversion completions to trigger the next PDB channel pre-trigger and trigger
outputs, so that the ADC conversions can be triggered on the next set of configuration
and results registers. When back-to-back operation is enabled by setting CHnC1[BB[m]],
then the delay m is ignored and the pre-trigger m is asserted 2 peripheral cycles after the
acknowledgment m is received. The acknowledgment connections in this MCU are
described in
Back-to-back acknowledgment connections
Functional description
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
810
Freescale Semiconductor, Inc.
