SIM_SOPT2[TRACECLKSEL]
TRACECLKIN
Core / system clock
MCGOUTCLK
Debug
Figure 5-3. Trace clock generation
5.7.5 PORT digital filter clocking
The digital filters in the PORTD module can be clocked as shown in the following figure.
NOTE
In stop mode, the digital input filters are bypassed unless they
are configured to run from the 1 kHz LPO clock source.
PORTx_DFCR[CS]
PORTx digital input
filter clock
Bus clock
LPO
Figure 5-4. PORTx digital input filter clock generation
5.7.6 LPTMR clocking
The prescaler and glitch filters in each of the LPTMRx modules can be clocked as shown
in the following figure.
NOTE
The chosen clock must remain enabled if the LPTMRx is to
continue operating in all required low-power modes.
Module clocks
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
158
Freescale Semiconductor, Inc.
