Table 5-1. Clock Summary (continued)
Clock name
High Speed Run
mode
clock frequency
Run mode
clock frequency
VLPR mode
clock frequency
Clock source
Clock is disabled
when…
LPUART0 clock
Up to 100 MHz
Up to 100MHz
Up to 16MHz
MCGFLLCLK or
IRC48MCLK or
MCGIRCLK or
OSCERCLK
LPUART0 is
disabled
5.5 Internal clocking requirements
The clock dividers are programmed via the SIM module’s CLKDIV registers. Each
divider is programmable from a divide-by-1 through divide-by-16 setting. The following
requirements must be met when configuring the clocks for this device:
1. The core and system clock frequencies must be 120 MHz or slower in HSRUN, 80
MHz or slower in RUN.
2. The bus clock frequency must be programmed to 60 MHz or less in HSRUN, 50
MHz or less in RUN, and an integer divide of the core clock. The core clock to bus
clock ratio is limited to a max value of 8.
3. The flash clock frequency must be programmed to 26.67 MHz or less, less than or
equal to the bus clock, and an integer divide of the core clock. The core clock to flash
clock ratio is limited to a max value of 8.
The following are a few of the more common clock configurations for this device:
Option 1:
Clock
Frequency
Core clock
50 MHz
System clock
50 MHz
Bus clock
50 MHz
Flash clock
25 MHz
Option 2: Run
Clock
Frequency
Core clock
80 MHz
System clock
80 MHz
Table continues on the next page...
Internal clocking requirements
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
152
Freescale Semiconductor, Inc.
