44.4.4.3 Continuous Selection Format
Some peripherals must be deselected between every transfer. Other peripherals must
remain selected between several sequential serial transfers. The Continuous Selection
Format provides the flexibility to handle the following case. The Continuous Selection
Format is enabled for the SPI configuration by setting the CONT bit in the SPI command.
When the CONT bit = 0, the module drives the asserted Chip Select signals to their idle
states in between frames. The idle states of the Chip Select signals are selected by the
PCSISn bits in the MCR. The following timing diagram is for two four-bit transfers with
CPHA = 1 and CONT = 0.
PCSx
SCK
Master SIN
tCSC = PCS to SCK dela
t
ASC =
After SCK delay
SCK (CPOL = 0)
SCK (CPOL = 1)
Master SOUT
t
DT =
Delay after Transfer (minimum CS negation time)
t
CSC
t
ASC
t
CSC
t
DT
Figure 44-74. Example of non-continuous format (CPHA=1, CONT=0)
When the CONT bit = 1, the PCS signal remains asserted for the duration of the two
transfers. The Delay between Transfers (t
DT
) is not inserted between the transfers. The
following figure shows the timing diagram for two four-bit transfers with CPHA = 1 and
CONT = 1.
Chapter 44 Serial Peripheral Interface (SPI)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
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