I2Sx_TCR2 field descriptions
Field
Description
31–30
SYNC
Synchronous Mode
Configures between asynchronous and synchronous modes of operation. When configured for a
synchronous mode of operation, the receiver must be configured for asynchronous operation.
00
Asynchronous mode.
01
Synchronous with receiver.
10
Synchronous with another SAI transmitter.
11
Synchronous with another SAI receiver.
29
BCS
Bit Clock Swap
This field swaps the bit clock used by the transmitter. When the transmitter is configured in asynchronous
mode and this bit is set, the transmitter is clocked by the receiver bit clock (SAI_RX_BCLK). This allows
the transmitter and receiver to share the same bit clock, but the transmitter continues to use the transmit
frame sync (SAI_TX_SYNC).
When the transmitter is configured in synchronous mode, the transmitter BCS field and receiver BCS field
must be set to the same value. When both are set, the transmitter and receiver are both clocked by the
transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync (SAI_RX_SYNC).
0
Use the normal bit clock source.
1
Swap the bit clock source.
28
BCI
Bit Clock Input
When this field is set and using an internally generated bit clock in either synchronous or asynchronous
mode, the bit clock actually used by the transmitter is delayed by the pad output delay (the transmitter is
clocked by the pad input as if the clock was externally generated). This has the effect of decreasing the
data input setup time, but increasing the data output valid time.
The slave mode timing from the datasheet should be used for the transmitter when this bit is set. In
synchronous mode, this bit allows the transmitter to use the slave mode timing from the datasheet, while
the receiver uses the master mode timing. This field has no effect when configured for an externally
generated bit clock .
0
No effect.
1
Internal logic is clocked as if bit clock was externally generated.
27–26
MSEL
MCLK Select
Selects the audio Master Clock option used to generate an internally generated bit clock. This field has no
effect when configured for an externally generated bit clock.
NOTE: Depending on the device, some Master Clock options might not be available. See the chip
configuration details for the availability and chip-specific meaning of each option.
00
Bus Clock selected.
01
Master Clock (MCLK) 1 option selected.
10
Master Clock (MCLK) 2 option selected.
11
Master Clock (MCLK) 3 option selected.
25
BCP
Bit Clock Polarity
Configures the polarity of the bit clock.
0
Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
1
Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
Table continues on the next page...
Memory map and register definition
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
1260
Freescale Semiconductor, Inc.
