Table 10-2. Ports summary (continued)
Feature
Port A
Port B
Port C
Port D
Port E
Pin mux control
Yes
Yes
Yes
Yes
Yes
Pin mux at reset
PTA0/PTA1/PTA2/
PTA3/PTA4=ALT7;
Others=ALT0
ALT0
ALT0
ALT0
ALT0
Lock bit
Yes
Yes
Yes
Yes
Yes
Interrupt and DMA
request
Yes
Yes
Yes
Yes
Yes
Digital glitch filter No
No
No
Yes
No
10.2.2 Clock gating
The clock to the port control module can be gated on and off using the SCGC5[PORTx]
bits in the SIM module. These bits are cleared after any reset, which disables the clock to
the corresponding module to conserve power. Prior to initializing the corresponding
module, set SCGC5[PORTx] in the SIM module to enable the clock. Before turning off
the clock, make sure to disable the module. For more details, refer to the clock
distribution chapter.
10.2.3 Signal multiplexing constraints
1. A given peripheral function must be assigned to a maximum of one package pin. Do
not program the same function to more than one pin.
2. To ensure the best signal timing for a given peripheral's interface, choose the pins in
closest proximity to each other.
10.3 Pinout
10.3.1 K22F Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
NOTE
The 64-pin MAPBGA package offering is subject to removal.
Chapter 10 Signal Multiplexing and Signal Descriptions
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
209
