FIFO is chosen for the illustration, but the concepts carry over. See
Out (TX FIFO) buffering mechanism
Receive First In First Out (RX FIFO) buffering
for details on the FIFO operation.
Push TX FIFO Register
Transmit Next
Data Pointer
Shift Register
SOUT
+1
-1
TX FIFO Counter
TX FIFO Base
-
Entry C
Entry A (first in)
Entry D (last in)
Entry B
-
-
-
Figure 44-78. TX FIFO pointers and counter
44.5.6.1 Address Calculation for the First-in Entry and Last-in Entry
in the TX FIFO
The memory address of the first-in entry in the TX FIFO is computed by the following
equation:
The memory address of the last-in entry in the TX FIFO is computed by the following
equation:
TX FIFO Base - Base address of TX FIFO
TXCTR - TX FIFO Counter
TXNXTPTR - Transmit Next Pointer
TX FIFO Depth - Transmit FIFO depth, implementation specific
Initialization/application information
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
1092
Freescale Semiconductor, Inc.
