The SWOCTRL register can be updated at each rising edge of system clock (SWOC = 0)
or by the enhanced PWM synchronization (SWOC = 1 and SYNCMODE = 1) according
to the following flowchart.
In the case of enhanced PWM synchronization, the SWOCTRL register synchronization
depends on SWSOC and HWSOC bits.
end
begin
= 1
= 0
end
end
end
end
end
= 1
= 0
= 1
= 1
= 0
= 0
= 1
SWOCTRL is updated
by software trigger
software
trigger
hardware
trigger
SWOCTRL is updated
by hardware trigger
enhanced PWM synchronization
update SWOCTRL register by
PWM synchronization
update SWOCTRL register at
each rising edge of system clock
= yes
0 =
1 =
0 =
0 =
no =
1 =
SWOC
bit ?
SYNCMODE
bit ?
rising edge
of system
clock ?
update SWOCTRL
with its buffer value
update SWOCTRL
with its buffer value
HWSOC
bit ?
TRIGn
bit ?
wait hardware trigger n
update SWOCTRL
with its buffer value
HWTRIGMODE
bit ?
clear TRIGn bit
SWSOC
bit ?
SWSYNC
bit ?
Figure 38-220. SWOCTRL register synchronization flowchart
Chapter 38 FlexTimer Module (FTM)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
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