49.2.6 Port Data Direction Register (GPIOx_PDDR)
The PDDR configures the individual port pins for input or output.
Address: Base a 14h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_PDDR field descriptions
Field
Description
31–0
PDD
Port Data Direction
Configures individual port pins for input or output.
0
Pin is configured as general-purpose input, for the GPIO function.
1
Pin is configured as general-purpose output, for the GPIO function.
49.3 Functional description
49.3.1 General-purpose input
The logic state of each pin is available via the Port Data Input registers, provided the pin
is configured for a digital function and the corresponding Port Control and Interrupt
module is enabled.
The Port Data Input registers return the synchronized pin state after any enabled digital
filter in the Port Control and Interrupt module. The input pin synchronizers are shared
with the Port Control and Interrupt module, so that if the corresponding Port Control and
Interrupt module is disabled, then synchronizers are also disabled. This reduces power
consumption when a port is not required for general-purpose input functionality.
49.3.2 General-purpose output
The logic state of each pin can be controlled via the port data output registers and port
data direction registers, provided the pin is configured for the GPIO function. The
following table depicts the conditions for a pin to be configured as input/output.
If
Then
Table continues on the next page...
Functional description
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
1296
Freescale Semiconductor, Inc.
