DMA_SEEI field descriptions (continued)
Field
Description
3–0
SEEI
Set Enable Error Interrupt
Sets the corresponding bit in EEI
22.3.7 Clear Enable Request Register (DMA_CERQ)
The CERQ provides a simple memory-mapped mechanism to clear a given bit in the
ERQ to disable the DMA request for a given channel. The data value on a register write
causes the corresponding bit in the ERQ to be cleared. Setting the CAER bit provides a
global clear function, forcing the entire contents of the ERQ to be cleared, disabling all
DMA request inputs. If NOP is set, the command is ignored. This allows you to write
multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
Address: 4000_8000h base + 1Ah offset = 4000_801Ah
Bit
7
6
5
4
3
2
1
0
Read
0
0
0
Write
Reset
0
0
0
0
0
0
0
0
DMA_CERQ field descriptions
Field
Description
7
NOP
No Op enable
0
Normal operation
1
No operation, ignore the other bits in this register
6
CAER
Clear All Enable Requests
0
Clear only the ERQ bit specified in the CERQ field
1
Clear all bits in ERQ
5–4
Reserved
This field is reserved.
3–0
CERQ
Clear Enable Request
Clears the corresponding bit in ERQ.
Chapter 22 Enhanced Direct Memory Access (eDMA)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
445
