Freescale Semiconductor MK22FN256VDC12, Reference Manual

Page: 426 / 1313

DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_9028
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD1_NBYTES_MLNO)
32 R/W Undefined 22.3.21/464
4000_9028
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD1_NBYTES_MLOFFNO)
32 R/W Undefined 22.3.22/465
4000_9028
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD1_NBYTES_MLOFFYES)
32 R/W Undefined 22.3.23/466
4000_902C
TCD Last Source Address Adjustment
(DMA_TCD1_SLAST)
32 R/W Undefined 22.3.24/467
4000_9030 TCD Destination Address (DMA_TCD1_DADDR) 32 R/W Undefined 22.3.25/468
4000_9034
TCD Signed Destination Address Offset
(DMA_TCD1_DOFF)
16 R/W Undefined 22.3.26/468
4000_9036
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD1_CITER_ELINKYES)
16 R/W Undefined 22.3.27/469
4000_9036 DMA_TCD1_CITER_ELINKNO 16 R/W Undefined 22.3.28/470
4000_9038
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD1_DLASTSGA)
32 R/W Undefined 22.3.29/471
4000_903C TCD Control and Status (DMA_TCD1_CSR) 16 R/W Undefined 22.3.30/472
4000_903E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD1_BITER_ELINKYES)
16 R/W Undefined 22.3.31/474
4000_903E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled) (DMA_TCD1_BITER_ELINKNO)
16 R/W Undefined 22.3.32/475
4000_9040 TCD Source Address (DMA_TCD2_SADDR) 32 R/W Undefined 22.3.18/462
4000_9044 TCD Signed Source Address Offset (DMA_TCD2_SOFF) 16 R/W Undefined 22.3.19/462
4000_9046 TCD Transfer Attributes (DMA_TCD2_ATTR) 16 R/W Undefined 22.3.20/463
4000_9048
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD2_NBYTES_MLNO)
32 R/W Undefined 22.3.21/464
4000_9048
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD2_NBYTES_MLOFFNO)
32 R/W Undefined 22.3.22/465
4000_9048
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD2_NBYTES_MLOFFYES)
32 R/W Undefined 22.3.23/466
4000_904C
TCD Last Source Address Adjustment
(DMA_TCD2_SLAST)
32 R/W Undefined 22.3.24/467
4000_9050 TCD Destination Address (DMA_TCD2_DADDR) 32 R/W Undefined 22.3.25/468
4000_9054
TCD Signed Destination Address Offset
(DMA_TCD2_DOFF)
16 R/W Undefined 22.3.26/468
4000_9056
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD2_CITER_ELINKYES)
16 R/W Undefined 22.3.27/469
4000_9056 DMA_TCD2_CITER_ELINKNO 16 R/W Undefined 22.3.28/470
4000_9058
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD2_DLASTSGA)
32 R/W Undefined 22.3.29/471
4000_905C TCD Control and Status (DMA_TCD2_CSR) 16 R/W Undefined 22.3.30/472
Table continues on the next page...
Memory map/register definition
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
426 Freescale Semiconductor, Inc.