Freescale Semiconductor MK22FN256VDC12, Reference Manual

Page: 1067 / 1313

In master mode, the register transfers 16 bits of data and 16 bits of command information
to the TX FIFO. In slave mode, all 32 register bits can be used as data, supporting up to
32-bit SPI Frame operation.
Address: Base a 34h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TXDATA
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPIx_PUSHR_SLAVE field descriptions
Field Description
31–0
TXDATA
Transmit Data
Holds SPI data to be transferred according to the associated SPI command.
44.3.9 POP RX FIFO Register (SPIx_POPR)
POPR is used to read the RX FIFO. Eight- or sixteen-bit read accesses to the POPR have
the same effect on the RX FIFO as 32-bit read accesses. A write to this register will
generate a Transfer Error.
Address: Base a 38h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RXDATA
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPIx_POPR field descriptions
Field Description
31–0
RXDATA
Received Data
Contains the SPI data from the RX FIFO entry to which the Pop Next Data Pointer points.
Chapter 44 Serial Peripheral Interface (SPI)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc. 1067