Table 25-16. MCG modes of operation (continued)
Mode
Description
FLL Bypassed External
(FBE)
FLL bypassed external (FBE) mode is entered when all the following conditions occur:
• 10 is written to C1[CLKS].
• 0 is written to C1[IREFS].
• C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25
kHz to 39.0625 kHz.
• 0 is written to C6[PLLS].
• 0 is written to C2[LP].
In FBE mode, the MCGOUTCLK is derived from the OSCSEL external reference clock. The FLL is
operational but its output is not used. This mode is useful to allow the FLL to acquire its target
frequency while the MCGOUTCLK is driven from the external reference clock. The FLL clock
(DCOCLK) is controlled by the external reference clock, and the DCO clock frequency locks to a
multiplication factor, as selected by C4[DRST_DRS] and C4[DMX32] bits, times the divided external
reference frequency. See the C4[DMX32] bit description for more details. In FBE mode, the PLL is
disabled in a low-power state unless C5[PLLCLKEN] is set .
PLL Engaged External
(PEE)
PLL Engaged External (PEE) mode is entered when all the following conditions occur:
• 00 is written to C1[CLKS].
• 0 is written to C1[IREFS].
• 1 is written to C6[PLLS].
In PEE mode, the MCGOUTCLK is derived from the output of PLL which is controlled by a external
reference clock. The PLL clock frequency locks to a multiplication factor, as specified by its
corresponding VDIV, times the selected PLL reference frequency, as specified by its corresponding
PRDIV. The PLL's programmable reference divider must be configured to produce a valid PLL
reference clock. The FLL is disabled in a low-power state.
PLL Bypassed External
(PBE)
PLL Bypassed External (PBE) mode is entered when all the following conditions occur:
• 10 is written to C1[CLKS].
• 0 is written to C1[IREFS].
• 1 is written to C6[PLLS].
• 0 is written to C2[LP].
In PBE mode, MCGOUTCLK is derived from the OSCSEL external reference clock; the PLL is
operational, but its output clock is not used. This mode is useful to allow the PLL to acquire its target
frequency while MCGOUTCLK is driven from the external reference clock. The PLL clock frequency
locks to a multiplication factor, as specified by its [VDIV], times the PLL reference frequency, as
specified by its [PRDIV]. In preparation for transition to PEE, the PLL's programmable reference
divider must be configured to produce a valid PLL reference clock. The FLL is disabled in a low-
power state.
Table continues on the next page...
Chapter 25 Multipurpose Clock Generator (MCG)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
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