UARTx_C2 field descriptions (continued)
Field
Description
is already idle, it is possible that the UART will discard data. This is because the data must be
received or a LIN break detected after an IDLE is detected before IDLE is allowed to reasserted.
0
Normal operation.
1
RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware
wakes the receiver by automatically clearing RWU.
0
SBK
Send Break
Toggling SBK sends one break character from the following: See
for the
number of logic 0s for the different configurations. Toggling implies clearing the SBK field before the break
character has finished transmitting. As long as SBK is set, the transmitter continues to send complete
break characters (10, 11, or 12 bits, or 13 or 14 bits). Ensure that C2[TE] is asserted atleast 1 clock before
assertion of this bit.
• 10, 11, or 12 logic 0s if S2[BRK13] is cleared
• 13 or 14 logic 0s if S2[BRK13] is set.
This field must be cleared when C7816[ISO_7816E] is set.
0
Normal transmitter operation.
1
Queue break characters to be sent.
46.3.5 UART Status Register 1 (UARTx_S1)
The S1 register provides inputs to the MCU for generation of UART interrupts or DMA
requests. This register can also be polled by the MCU to check the status of its fields. To
clear a flag, the status register should be read followed by a read or write to D register,
depending on the interrupt flag type. Other instructions can be executed between the two
steps as long the handling of I/O is not compromised, but the order of operations is
important for flag clearing. When a flag is configured to trigger a DMA request, assertion
of the associated DMA done signal from the DMA controller clears the flag.
NOTE
• If the condition that results in the assertion of the flag,
interrupt, or DMA request is not resolved prior to clearing
the flag, the flag, and interrupt/DMA request, reasserts. For
example, if the DMA or interrupt service routine fails to
write sufficient data to the transmit buffer to raise it above
the watermark level, the flag reasserts and generates
another interrupt or DMA request.
• Reading an empty data register to clear one of the flags of
the S1 register causes the FIFO pointers to become
misaligned. A receive FIFO flush reinitializes the pointers.
A better way to prevent this situation is to always leave one
Chapter 46 Universal Asynchronous Receiver/Transmitter (UART)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
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