48.1.3.2 Stop modes
In Stop mode, the SAI transmitter and/or receiver can continue operating provided the
appropriate Stop Enable bit is set (TCSR[STOPE] and/or RCSR[STOPE], respectively),
and provided the transmitter and/or receiver is/are using an externally generated bit clock
or an Audio Master Clock that remains operating in Stop mode. The SAI transmitter and/
or receiver can generate an asynchronous interrupt to wake the CPU from Stop mode.
In Stop mode, if the Transmitter Stop Enable (TCSR[STOPE]) bit is clear, the transmitter
is disabled after completing the current transmit frame, and, if the Receiver Stop Enable
(RCSR[STOPE]) bit is clear, the receiver is disabled after completing the current receive
frame. Entry into Stop mode is prevented–not acknowledged–while waiting for the
transmitter and receiver to be disabled at the end of the current frame.
48.1.3.3 Low-leakage modes
When entering low-leakage modes, the Stop Enable (TCSR[STOPE] and
RCSR[STOPE]) bits are ignored and the SAI is disabled after completing the current
transmit and receive Frames. Entry into stop mode is prevented (not acknowledged)
while waiting for the transmitter and receiver to be disabled at the end of the current
frame.
48.1.3.4 Debug mode
In Debug mode, the SAI transmitter and/or receiver can continue operating provided the
Debug Enable bit is set. When TCSR[DBGE] or RCSR[DBGE] bit is clear and Debug
mode is entered, the SAI is disabled after completing the current transmit or receive
frame. The transmitter and receiver bit clocks are not affected by Debug mode.
48.2 External signals
Name
Function
I/O
SAI_TX_BCLK
Transmit Bit Clock. The bit clock is an input when
externally generated and an output when
internally generated.
I/O
Table continues on the next page...
Chapter 48 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
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