FTMx_COMBINE field descriptions (continued)
Field
Description
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0
The Dual Edge Capture mode in this pair of channels is disabled.
1
The Dual Edge Capture mode in this pair of channels is enabled.
9
COMP1
Complement Of Channel (n) For n = 2
Enables Complementary mode for the combined channels. In Complementary mode the channel (n+1)
output is the inverse of the channel (n) output.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0
The channel (n+1) output is the same as the channel (n) output.
1
The channel (n+1) output is the complement of the channel (n) output.
8
COMBINE1
Combine Channels For n = 2
Enables the combine feature for channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0
Channels (n) and (n+1) are independent.
1
Channels (n) and (n+1) are combined.
7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6
FAULTEN0
Fault Control Enable For n = 0
Enables the fault control in channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0
The fault control in this pair of channels is disabled.
1
The fault control in this pair of channels is enabled.
5
SYNCEN0
Synchronization Enable For n = 0
Enables PWM synchronization of registers C(n)V and C(n+1)V.
0
The PWM synchronization in this pair of channels is disabled.
1
The PWM synchronization in this pair of channels is enabled.
4
DTEN0
Deadtime Enable For n = 0
Enables the deadtime insertion in the channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0
The deadtime insertion in this pair of channels is disabled.
1
The deadtime insertion in this pair of channels is enabled.
3
DECAP0
Dual Edge Capture Mode Captures For n = 0
Enables the capture of the FTM counter value according to the channel (n) input event and the
configuration of the dual edge capture bits.
This field applies only when DECAPEN = 1.
DECAP bit is cleared automatically by hardware if dual edge capture – one-shot mode is selected and
when the capture of channel (n+1) event is made.
0
The dual edge captures are inactive.
1
The dual edge captures are active.
Table continues on the next page...
Memory map and register definition
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
846
Freescale Semiconductor, Inc.
