Freescale Semiconductor MK22FN256VDC12, Reference Manual

Page: 750 / 1313

• If enabled, the Filter block will incur up to one bus clock additional latency penalty
on COUT due to the fact that COUT, which is crossing clock domain boundaries,
must be resynchronized to the bus clock.
• CR1[WE] and CR1[SE] are mutually exclusive.
34.2 Memory map/register definitions
CMP memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_3000 CMP Control Register 0 (CMP0_CR0) 8 R/W 00h 34.2.1/750
4007_3001 CMP Control Register 1 (CMP0_CR1) 8 R/W 00h 34.2.2/751
4007_3002 CMP Filter Period Register (CMP0_FPR) 8 R/W 00h 34.2.3/753
4007_3003 CMP Status and Control Register (CMP0_SCR) 8 R/W 00h 34.2.4/753
4007_3004 DAC Control Register (CMP0_DACCR) 8 R/W 00h 34.2.5/754
4007_3005 MUX Control Register (CMP0_MUXCR) 8 R/W 00h 34.2.6/755
4007_3008 CMP Control Register 0 (CMP1_CR0) 8 R/W 00h 34.2.1/750
4007_3009 CMP Control Register 1 (CMP1_CR1) 8 R/W 00h 34.2.2/751
4007_300A CMP Filter Period Register (CMP1_FPR) 8 R/W 00h 34.2.3/753
4007_300B CMP Status and Control Register (CMP1_SCR) 8 R/W 00h 34.2.4/753
4007_300C DAC Control Register (CMP1_DACCR) 8 R/W 00h 34.2.5/754
4007_300D MUX Control Register (CMP1_MUXCR) 8 R/W 00h 34.2.6/755
34.2.1 CMP Control Register 0 (CMPx_CR0)
Address: Base a 0h offset
Bit 7 6 5 4 3 2 1 0
Read 0
FILTER_CNT
0 0
HYSTCTR
Write
Reset
0 0 0 0 0 0 0 0
CMPx_CR0 field descriptions
Field Description
7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6–4
FILTER_CNT
Filter Sample Count
Table continues on the next page...
Memory map/register definitions
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
750 Freescale Semiconductor, Inc.