Freescale Semiconductor MK22FN256VDC12, Reference Manual

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or 16-bit writes to the transmit data field. This allows a single 16-bit write to the
command word to be used for all subsequent 8-bit or 16-bit writes to the transmit data
word. Writing a different 16-bit command word will cause all subsequent 8-bit or 16-bit
writes to the transmit data word to be pushed to the TX FIFO with the new command
word.
3.9.3 I2C Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Signal
multiplexing
Register
access
Peripheral
bridge
Module signals
2
I C
Figure 3-51. I2C configuration
Table 3-66. Reference links to related information
Topic Related module Reference
Full description I2C I2C
System memory map System memory map
Clocking Clock Distribution
Power management Power management
Signal Multiplexing Port control Signal Multiplexing
3.9.3.1 I2C Instantiation Information
This device has two I
2
C modules.
The I2C module includes SMBus support and DMA support. It also has optional address
match wakeup in Stop/VLPS mode.
The digital glitch filter implemented in the IIC module, controlled by the
I2Cx_FLT[FLT] registers, is clocked from the bus clock and thus has filter granularity in
bus clock cycle counts.
Chapter 3 Chip Configuration
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc. 127