generate packets. If multiple sources generate packets at the same time, the ITM
arbitrates the order in which packets are output. The four sources in decreasing order of
priority are:
1. Software trace -- Software can write directly to ITM stimulus registers. This emits
packets.
2. Hardware trace -- The DWT generates these packets, and the ITM emits them.
3. Time stamping -- Timestamps are emitted relative to packets. The ITM contains a
21-bit counter to generate the timestamp. The Cortex-M4 clock or the bitclock rate of
the Serial Wire Viewer (SWV) output clocks the counter.
4. Global system timestamping. Timestamps can optionally be generated using a
system-wide 48-bit count value.
9.9 Core Trace Connectivity
The ITM can route its data to the TPIU. (See the
MCM (Miscellaneous Control Module)
for controlling the routing to the TPIU.) This configuration enables the use of trace with
low cost tools while maintaining the compatibility with trace probes.
9.10 TPIU
The TPIU acts as a bridge between the on-chip trace data from the Instrumentation Trace
Macrocell (ITM) to a data stream, encapsulating IDs where required, that is then captured
by a Trace Port Analyzer (TPA). The TPIU is specially designed for low-cost debug.
9.11 DWT
The DWT is a unit that performs the following debug functionality:
• It contains four comparators that you can configure as a hardware watchpoint, a PC
sampler event trigger, or a data address sampler event trigger. The first comparator,
DWT_COMP0, can also compare against the clock cycle counter, CYCCNT. The
second comparator, DWT_COMP1, can also be used as a data comparator.
• The DWT contains counters for:
• Clock cycles (CYCCNT)
• Folded instructions
• Load store unit (LSU) operations
• Sleep cycles
Core Trace Connectivity
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Freescale Semiconductor, Inc.
