47.2.1 LPUART Baud Rate Register (LPUARTx_BAUD)
Address: 4002_A000h base + 0h offset = 4002_A000h
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
Reset
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
LPUARTx_BAUD field descriptions
Field
Description
31
MAEN1
Match Address Mode Enable 1
0
Normal operation.
1
Enables automatic address matching or data matching mode for MATCH[MA1].
30
MAEN2
Match Address Mode Enable 2
0
Normal operation.
1
Enables automatic address matching or data matching mode for MATCH[MA2].
29
M10
10-bit Mode select
The M10 bit causes a tenth bit to be part of the serial transmission. This bit should only be changed when
the transmitter and receiver are both disabled.
0
Receiver and transmitter use 8-bit or 9-bit data characters.
1
Receiver and transmitter use 10-bit data characters.
28–24
OSR
Over Sampling Ratio
This field configures the oversampling ratio for the receiver between 4x (00011) and 32x (11111). Writing
an invalid oversampling ratio will default to an oversampling ratio of 16 (01111). This field should only be
changed when the transmitter and receiver are both disabled.
23
TDMAE
Transmitter DMA Enable
TDMAE configures the transmit data register empty flag, LPUART_STAT[TDRE], to generate a DMA
request.
0
DMA request disabled.
1
DMA request enabled.
Table continues on the next page...
Chapter 47 Low Power Universal asynchronous receiver/transmitter (LPUART)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
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