GPIO memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
400F_F108 Port Clear Output Register (GPIOE_PCOR)
32
W
(always
reads 0)
0000_0000h
400F_F10C Port Toggle Output Register (GPIOE_PTOR)
32
W
(always
reads 0)
0000_0000h
400F_F110 Port Data Input Register (GPIOE_PDIR)
32
R
0000_0000h
400F_F114 Port Data Direction Register (GPIOE_PDDR)
32
R/W
0000_0000h
49.2.1 Port Data Output Register (GPIOx_PDOR)
This register configures the logic levels that are driven on each general-purpose output
pins.
NOTE
Do not modify pin configuration registers associated with pins
not available in your selected package. All unbonded pins not
available in your package will default to DISABLE state for
lowest power consumption.
Address: Base a 0h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_PDOR field descriptions
Field
Description
31–0
PDO
Port Data Output
Register bits for unbonded pins return a undefined value when read.
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
Chapter 49 General-Purpose Input/Output (GPIO)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
1293
